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boards: Add support for NXP board mimxt595_evk

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Add support for mimxrt595_evk

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit is contained in:
Mahesh Mahadevan 2022-01-07 11:33:12 -06:00 • committed by David Leach
commit 83af6e6374
11 changed files with 712 additions and 0 deletions
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boards/arm/mimxrt595_evk/CMakeLists.txt Normal file
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#
# Copyright (c) 2022, NXP
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_library()
zephyr_library_sources(pinmux.c)
zephyr_include_directories(.)

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boards/arm/mimxrt595_evk/Kconfig.board Normal file
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# Copyright (c) 2022, NXP
# SPDX-License-Identifier: Apache-2.0
config BOARD_MIMXRT595_EVK
bool "NXP MIMXRT595-EVK"
depends on SOC_SERIES_IMX_RT5XX
select CODE_DATA_RELOCATION_SRAM
select SOC_PART_NUMBER_MIMXRT595SFFOC
select NXP_IMX_RT5XX_BOOT_HEADER if !BOOTLOADER_MCUBOOT

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boards/arm/mimxrt595_evk/Kconfig.defconfig Normal file
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# MIMXRT595-EVK board
# Copyright (c) 2022, NXP
# SPDX-License-Identifier: Apache-2.0
if BOARD_MIMXRT595_EVK
config BOARD
default "mimxrt595_evk_cm33"
config FLASH_SIZE
default $(dt_node_int_prop_int,/soc/spi@134000/mx25um51345g@2,size,K)
endif # BOARD_MIMXRT595_EVK

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boards/arm/mimxrt595_evk/board.cmake Normal file
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#
# Copyright (c) 2022, NXP
#
# SPDX-License-Identifier: Apache-2.0
#
board_runner_args(jlink "--device=MIMXRT595S_M33" "--reset-after-load")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

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.. _mimxrt595_evk:
NXP MIMXRT595-EVK
##################
Overview
********
i.MX RT500 crossover MCUs are part of the edge computing family and are optimized
for low-power HMI applications by combining a graphics engine and a streamlined
Cadence Tensilica Fusion F1 DSP core with a next-generation Arm Cortex-M33
core. These devices are designed to unlock the potential of display-based applications
with a secure, power-optimized embedded processor.
i.MX RT500 MCUs provides up to 5MB of on-chip SRAM and several high-bandwidth interfaces
to access off-chip flash, including an Octal/Quad SPI interface with an on-the-fly
decryption engine.
.. image:: ./mimxrt595_evk.png
:width: 720px
:align: center
:alt: MIMXRT595-EVK
Hardware
********
- MIMXRT595SFFOC Cortex-M33 (275 MHz) core processor with Cadence Tensilica Fusion F1 DSP
- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug only)
- USB2.0 high-speed host and device with micro USB connector and external crystal
- Octal/Quad/pSRAM external memories via FlexSPI
- 5 MB system SRAM
- Full size SD card slot (SDIO)
- On-board eMMC chip
- On-board 5 V inputs NXP PCA9420UK PMIC providing 1.2 V, 1.8 V, 3.3 V
- User LEDs
- Reset and User buttons
- MIPI-DSI connector
- Single row headers for ARDUINO signals and MikroBus connector
- FlexIO connector for MikroElektronica TFT Proto 5 inch capacitive touch display
- One motion sensor combo accelero-/magneto-meter NXP FXOS8700CQ
- Stereo audio codec with line-In/ line-Out/ and Microphone
- Pmod/host expansion connector
- NXP TFA9896 audio digital amplifier
- Support for up to eight off-board digital microphones via 12-pin header
- Two on-board digital microphones
For more information about the MIMXRT595 SoC and MIMXRT595-EVK board, see
these references:
- `i.MX RT595 Website`_
- `i.MX RT595 Datasheet`_
- `i.MX RT595 Reference Manual`_
- `MIMXRT595-EVK Website`_
- `MIMXRT595-EVK User Guide`_
- `MIMXRT595-EVK Schematics`_
Supported Features
==================
The mimxrt595_evk board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| OS_TIMER | on-chip | os timer |
+-----------+------------+-------------------------------------+
| IOCON | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| USART | on-chip | serial port-polling |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/arm/mimxrt595_evk/mimxrt595_evk_cm33_defconfig``
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The MIMXRT595 SoC has IOCON registers, which can be used to configure the
functionality of a pin.
+---------+-----------------+----------------------------+
| Name | Function | Usage |
+=========+=================+============================+
| PIO0_2 | USART0 | USART RX |
+---------+-----------------+----------------------------+
| PIO0_1 | USART0 | USART TX |
+---------+-----------------+----------------------------+
| PIO0_14 | GPIO | GREEN LED |
+---------+-----------------+----------------------------+
| PIO0_25 | GPIO | SW0 |
+---------+-----------------+----------------------------+
| PIO0_10 | GPIO | SW1 |
+---------+-----------------+----------------------------+
| PIO4_30 | USART12 | USART TX |
+---------+-----------------+----------------------------+
| PIO4_31 | USART12 | USART RX |
+---------+-----------------+----------------------------+
System Clock
============
The MIMXRT595 EVK is configured to use the OS Event timer
as a source for the system clock.
Serial Port
===========
The MIMXRT595 SoC has 13 FLEXCOMM interfaces for serial communication. One is
configured as USART for the console and the remaining are not used.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the LPC-Link2.
.. tabs::
.. group-tab:: LPCLink2 JLink Onboard
1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path.
2. To connect the SWD signals to onboard debug circuit, install jumpers JP17, JP18 and JP19,
if not already done (these jumpers are installed by default).
3. Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program the
J-Link firmware. Please make sure you have the latest firmware for this board.
.. group-tab:: JLink External
1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path.
2. To disconnect the SWD signals from onboard debug circuit, **remove** jumpers J17, J18,
and J19 (these are installed by default).
3. Connect the J-Link probe to J2 10-pin header.
See :ref:`jlink-external-debug-probe` for more information.
Configuring a Console
=====================
Connect a USB cable from your PC to J40, and use the serial terminal of your choice
(minicom, putty, etc.) with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application. This example uses the
:ref:`jlink-debug-host-tools` as default.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt595_evk_cm33
:goals: flash
Open a serial terminal, reset the board (press the RESET button), and you should
see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS v2.7 ***
Hello World! mimxrt595_evk_cm33
Debugging
=========
Here is an example for the :ref:`hello_world` application. This example uses the
:ref:`jlink-debug-host-tools` as default.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt595_evk_cm33
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS v2.7 ***
Hello World! mimxrt595_evk_cm33
Troubleshooting
===============
If the debug probe fails to connect with the following error, it's possible
that the image in flash is interfering and causing this issue.
.. code-block:: console
Remote debugging using :2331
Remote communication error. Target disconnected.: Connection reset by peer.
"monitor" command not supported by this target.
"monitor" command not supported by this target.
You can't do that when your target is `exec'
(gdb) Could not connect to target.
Please check power, connection and settings.
You can fix it by erasing and reprogramming the flash with the following
steps:
#. Set the SW7 DIP switches to ON-ON-ON to prevent booting from flash.
#. Reset by pressing SW3
#. Run ``west debug`` or ``west flash`` again with a known working Zephyr
application (example "Hello World").
#. Set the SW5 DIP switches to OFF-OFF-ON to boot from flash.
#. Reset by pressing SW3
.. _MIMXRT595-EVK Website:
https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt595-evaluation-kit:MIMXRT595-EVK
.. _MIMXRT595-EVK User Guide:
https://www.nxp.com/webapp/Download?colCode=MIMXRT595EVKHUG
.. _MIMXRT595-EVK Schematics:
https://www.nxp.com/downloads/en/schematics/MIMXRT595-EVK-DESIGN-FILES.zip
.. _i.MX RT595 Website:
https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt500-crossover-mcu-with-arm-cortex-m33-dsp-and-gpu-cores:i.MX-RT500
.. _i.MX RT595 Datasheet:
https://www.nxp.com/docs/en/data-sheet/IMXRT500EC.pdf
.. _i.MX RT595 Reference Manual:
https://www.nxp.com/webapp/Download?colCode=IMXRT500RM

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boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts Normal file
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/*
* Copyright (c) 2022, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nxp/nxp_rt5xx.dtsi>
/ {
model = "NXP MIMXRT595-EVK board";
compatible = "nxp,mimxrt595";
aliases {
sw0 = &user_button_1;
sw1 = &user_button_2;
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
usart-0 = &flexcomm0;
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &flexcomm0;
zephyr,shell-uart = &flexcomm0;
};
gpio_keys {
compatible = "gpio-keys";
user_button_1: button_0 {
label = "User SW1";
gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
};
user_button_2: button_1 {
label = "User SW2";
gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
green_led: led_1 {
gpios = <&gpio1 0 0>;
label = "User LED_GREEN";
};
blue_led: led_2 {
gpios = <&gpio3 17 0>;
label = "User LED_BLUE";
};
red_led: led_3 {
gpios = <&gpio0 14 0>;
label = "User LED_RED";
};
};
arduino_header: arduino-connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 5 0>, /* A0 */
<1 0 &gpio0 6 0>, /* A1 */
<2 0 &gpio0 19 0>, /* A2 */
<3 0 &gpio0 13 0>, /* A3 */
<4 0 &gpio4 22 0>, /* A4 */
<5 0 &gpio4 21 0>, /* A5 */
<6 0 &gpio4 31 0>, /* D0 */
<7 0 &gpio4 30 0>, /* D1 */
<8 0 &gpio4 20 0>, /* D2 */
<9 0 &gpio4 23 0>, /* D3 */
<10 0 &gpio4 24 0>, /* D4 */
<11 0 &gpio4 25 0>, /* D5 */
<12 0 &gpio4 26 0>, /* D6 */
<13 0 &gpio4 27 0>, /* D7 */
<14 0 &gpio4 28 0>, /* D8 */
<15 0 &gpio4 29 0>, /* D9 */
<16 0 &gpio5 0 0>, /* D10 */
<17 0 &gpio5 1 0>, /* D11 */
<18 0 &gpio5 2 0>, /* D12 */
<19 0 &gpio5 3 0>, /* D13 */
<20 0 &gpio4 22 0>, /* D14 */
<21 0 &gpio4 21 0>; /* D15 */
};
};
/*
* RT595 EVK board uses OS timer as the kernel timer
* In case we need to switch to SYSTICK timer, then
* replace &os_timer with &systick
*/
&os_timer {
status = "okay";
};
&flexcomm0 {
compatible = "nxp,lpc-usart";
status = "okay";
current-speed = <115200>;
};
arduino_serial: &flexcomm12 {
compatible = "nxp,lpc-usart";
status = "okay";
current-speed = <115200>;
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&gpio4 {
status = "okay";
};
&gpio5 {
status = "okay";
};
&gpio6 {
status = "okay";
};
&user_button_1 {
status = "okay";
};
&user_button_2 {
status = "okay";
};
&green_led {
status = "okay";
};
&blue_led {
status = "okay";
};
&red_led {
status = "okay";
};
&flexspi {
mx25um51345g: mx25um51345g@2 {
compatible = "nxp,imx-flexspi-mx25um51345g";
size = <DT_SIZE_M(64)>;
label = "MX25UM51345G";
reg = <2>;
spi-max-frequency = <200000000>;
status = "okay";
jedec-id = [c2 81 3a];
erase-block-size = <4096>;
write-block-size = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_M(24)>;
};
slot1_partition: partition@1810000 {
label = "image-1";
reg = <0x01810000 DT_SIZE_M(24)>;
};
scratch_partition: partition@3010000 {
label = "image-scratch";
reg = <0x03010000 DT_SIZE_K(8128)>;
};
storage_partition: partition@3f00000 {
label = "storage";
reg = <0x03f00000 DT_SIZE_M(1)>;
};
};
};
};

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boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml Normal file
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#
# Copyright (c) 2022, NXP
#
# SPDX-License-Identifier: Apache-2.0
#
identifier: mimxrt595_evk_cm33
name: NXP MIMXRT595-EVK
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 4608
flash: 65536
supported:
- arduino_gpio
- arduino_serial
- gpio

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boards/arm/mimxrt595_evk/mimxrt595_evk_cm33_defconfig Normal file
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#
# Copyright (c) 2022, NXP
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_SOC_MIMXRT595S_CM33=y
CONFIG_SOC_SERIES_IMX_RT5XX=y
CONFIG_BOARD_MIMXRT595_EVK=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_GPIO=y
# Enable TrustZone-M
CONFIG_TRUSTED_EXECUTION_SECURE=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y

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/*
* Copyright (c) 2022, NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <init.h>
#include <fsl_iopctl.h>
#include <soc.h>
static int mimxrt595_evk_pinmux_init(const struct device *dev)
{
ARG_UNUSED(dev);
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay) && CONFIG_SERIAL
/* USART0 RX, TX */
uint32_t port0_pin1_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */
IOPCTL_PIO_FUNC1 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Disable input buffer function */
IOPCTL_PIO_INBUF_DI |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT0 PIN1 (coords: G2) is configured as FC0_TXD_SCL_MISO_WS */
IOPCTL_PinMuxSet(IOPCTL, 0U, 1U, port0_pin1_config);
uint32_t port0_pin2_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */
IOPCTL_PIO_FUNC1 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT0 PIN2 (coords: G4) is configured as FC0_RXD_SDA_MOSI_DATA */
IOPCTL_PinMuxSet(IOPCTL, 0U, 2U, port0_pin2_config);
#endif
#if DT_PHA_HAS_CELL(DT_ALIAS(sw0), gpios, pin)
uint32_t port0_pin25_config = (/* Pin is configured as PIO0_25 */
IOPCTL_PIO_FUNC0 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT0 PIN25 (coords: C12) is configured as PIO0_25 */
IOPCTL_PinMuxSet(IOPCTL, 0U, 25U, port0_pin25_config);
#endif
#if DT_PHA_HAS_CELL(DT_ALIAS(sw1), gpios, pin)
uint32_t port0_pin10_config = (/* Pin is configured as PIO0_10 */
IOPCTL_PIO_FUNC0 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT0 PIN10 (coords: J3) is configured as PIO0_10 */
IOPCTL_PinMuxSet(IOPCTL, 0U, 10U, port0_pin10_config);
#endif
#ifdef DT_GPIO_LEDS_LED_3_GPIOS_CONTROLLER
uint32_t port0_pin14_config = (/* Pin is configured as PIO0_14 */
IOPCTL_PIO_FUNC0 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Disable input buffer function */
IOPCTL_PIO_INBUF_DI |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT0 PIN14 (coords: B12) is configured as PIO0_14 */
IOPCTL_PinMuxSet(IOPCTL, 0U, 14U, port0_pin14_config);
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm12), nxp_lpc_usart, okay) && CONFIG_SERIAL
/* USART12 RX, TX */
const uint32_t port4_pin30_config = (/* Pin is configured as FC12_TXD_SCL_MISO */
IOPCTL_PIO_FUNC6 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Disable input buffer function */
IOPCTL_PIO_INBUF_DI |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT4 PIN30 (coords: N8) is configured as FC12_TXD_SCL_MISO */
IOPCTL_PinMuxSet(IOPCTL, 4U, 30U, port4_pin30_config);
const uint32_t port4_pin31_config = (/* Pin is configured as FC12_RXD_SDA_MOSI */
IOPCTL_PIO_FUNC6 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Disable input buffer function */
IOPCTL_PIO_INBUF_DI |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT4 PIN31 (coords: N10) is configured as FC12_RXD_SDA_MOSI */
IOPCTL_PinMuxSet(IOPCTL, 4U, 31U, port4_pin31_config);
#endif
return 0;
}
/* priority set to CONFIG_PINMUX_INIT_PRIORITY value */
SYS_INIT(mimxrt595_evk_pinmux_init, PRE_KERNEL_1, 45);

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# Copyright (c) 2022, NXP
# SPDX-License-Identifier: Apache-2.0
# Suppress "simple_bus_reg" on RT5XX boards as all GPIO ports use the same register.
list(APPEND EXTRA_DTC_FLAGS "-Wno-simple_bus_reg")