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soc: fvp_aemv8r_aarch32: enable caches at init

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Enable at SoC boot time when enabled through Kconfig. Cache management
API is not used since it could be built without its support enabled.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles 2023-03-18 00:00:00 +00:00 • committed by Carles Cufí
commit 83613baf4a
3 changed files with 29 additions and 0 deletions
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1
soc/arm/arm/fvp_aemv8r_aarch32/CMakeLists.txt
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@ -2,3 +2,4 @@
# SPDX-License-Identifier: Apache-2.0 # SPDX-License-Identifier: Apache-2.0
zephyr_library_sources_ifdef(CONFIG_ARM_MPU arm_mpu_regions.c) zephyr_library_sources_ifdef(CONFIG_ARM_MPU arm_mpu_regions.c)
zephyr_library_sources(soc.c)

1
soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.soc
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@ -12,5 +12,6 @@ config SOC_FVP_AEMV8R_AARCH32
select CPU_HAS_MPU select CPU_HAS_MPU
select GIC_V3 select GIC_V3
select GIC_SINGLE_SECURITY_STATE select GIC_SINGLE_SECURITY_STATE
select PLATFORM_SPECIFIC_INIT
endchoice endchoice

27
soc/arm/arm/fvp_aemv8r_aarch32/soc.c Normal file
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@ -0,0 +1,27 @@
/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
void z_arm_platform_init(void)
{
if (IS_ENABLED(CONFIG_ICACHE)) {
if (!(__get_SCTLR() & SCTLR_I_Msk)) {
L1C_InvalidateICacheAll();
__set_SCTLR(__get_SCTLR() | SCTLR_I_Msk);
__ISB();
}
}
if (IS_ENABLED(CONFIG_DCACHE)) {
if (!(__get_SCTLR() & SCTLR_C_Msk)) {
L1C_InvalidateDCacheAll();
__set_SCTLR(__get_SCTLR() | SCTLR_C_Msk);
__DSB();
}
}
}