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boards: arm: Enable RTC backup RAM on some boards

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This patch enables STM32 RTC BBRAM in DTS on some STM32 boards for
testing purposes.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
This commit is contained in:
Patryk Duda 2022-12-02 18:38:52 +01:00 • committed by Stephanos Ioannidis
commit 82d26da680
8 changed files with 62 additions and 0 deletions
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4
boards/arm/nucleo_wb55rg/nucleo_wb55rg.dts
View file

@ -150,6 +150,10 @@
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>, clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>; <&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay"; status = "okay";
backup_regs {
status = "okay";
};
}; };
&spi1 { &spi1 {

14
boards/arm/stm32f0_disco/stm32f0_disco.dts
View file

@ -48,6 +48,10 @@
}; };
}; };
&clk_lsi {
status = "okay";
};
&clk_hse { &clk_hse {
clock-frequency = <DT_FREQ_M(8)>; clock-frequency = <DT_FREQ_M(8)>;
status = "okay"; status = "okay";
@ -120,3 +124,13 @@
&iwdg { &iwdg {
status = "okay"; status = "okay";
}; };
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
backup_regs {
status = "okay";
};
};

4
boards/arm/stm32f3_disco/stm32f3_disco.dts
View file

@ -170,6 +170,10 @@ zephyr_udc0: &usb {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>; <&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay"; status = "okay";
backup_regs {
status = "okay";
};
}; };
&can1 { &can1 {

4
boards/arm/stm32f4_disco/stm32f4_disco.dts
View file

@ -112,6 +112,10 @@
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>; <&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay"; status = "okay";
backup_regs {
status = "okay";
};
}; };
zephyr_udc0: &usbotg_fs { zephyr_udc0: &usbotg_fs {

4
boards/arm/stm32f746g_disco/stm32f746g_disco.dts
View file

@ -143,6 +143,10 @@ zephyr_udc0: &usbotg_fs {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>; <&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay"; status = "okay";
backup_regs {
status = "okay";
};
}; };
&sdmmc1 { &sdmmc1 {

14
boards/arm/stm32h735g_disco/stm32h735g_disco.dts
View file

@ -55,6 +55,10 @@
status = "okay"; status = "okay";
}; };
&clk_lsi {
status = "okay";
};
&pll { &pll {
div-m = <5>; div-m = <5>;
mul-n = <110>; mul-n = <110>;
@ -150,3 +154,13 @@
}; };
}; };
}; };
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
backup_regs {
status = "okay";
};
};

14
boards/arm/stm32l1_disco/stm32l1_disco.dts
View file

@ -46,6 +46,10 @@
}; };
}; };
&clk_lsi {
status = "okay";
};
&clk_hsi { &clk_hsi {
status = "okay"; status = "okay";
}; };
@ -114,3 +118,13 @@
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
}; };
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
backup_regs {
status = "okay";
};
};

4
boards/arm/stm32l476g_disco/stm32l476g_disco.dts
View file

@ -102,4 +102,8 @@
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>, clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>; <&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay"; status = "okay";
backup_regs {
status = "okay";
};
}; };