diff --git a/boards/arm/hexiwear_k64/Kconfig.defconfig b/boards/arm/hexiwear_k64/Kconfig.defconfig
index bf40e863788..16f97488975 100644
--- a/boards/arm/hexiwear_k64/Kconfig.defconfig
+++ b/boards/arm/hexiwear_k64/Kconfig.defconfig
@@ -10,12 +10,16 @@ if BOARD_HEXIWEAR_K64
 config BOARD
 	default hexiwear_k64
 
+if !HAS_DTS
+
 config FLASH_SIZE
 	default 1024
 
 config SRAM_SIZE
 	default 192
 
+endif # !HAS_DTS
+
 config OSC_XTAL0_FREQ
 	default 12000000
 
diff --git a/boards/arm/hexiwear_k64/hexiwear_k64_defconfig b/boards/arm/hexiwear_k64/hexiwear_k64_defconfig
index 7501e33b1ee..dc60165ee25 100644
--- a/boards/arm/hexiwear_k64/hexiwear_k64_defconfig
+++ b/boards/arm/hexiwear_k64/hexiwear_k64_defconfig
@@ -9,3 +9,4 @@ CONFIG_CORTEX_M_SYSTICK=y
 CONFIG_GPIO=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
 CONFIG_OSC_LOW_POWER=y
+CONFIG_HAS_DTS=y
diff --git a/dts/arm/Makefile b/dts/arm/Makefile
index 33350a2a893..fb604da20d9 100644
--- a/dts/arm/Makefile
+++ b/dts/arm/Makefile
@@ -1,4 +1,5 @@
 ifeq ($(CONFIG_HAS_DTS),y)
 dtb-$(CONFIG_BOARD_FRDM_K64F)	=	frdm_k64f.dts_compiled
+dtb-$(CONFIG_BOARD_HEXIWEAR_K64)	=	hexiwear_k64.dts_compiled
 always	:= $(dtb-y)
 endif
diff --git a/dts/arm/hexiwear_k64.dts b/dts/arm/hexiwear_k64.dts
new file mode 100644
index 00000000000..c83b1fa50c3
--- /dev/null
+++ b/dts/arm/hexiwear_k64.dts
@@ -0,0 +1,34 @@
+/dts-v1/;
+
+#include "nxp_k6x.dtsi"
+
+/ {
+	model = "Hexiwear K64  board";
+	compatible = "nxp,hexiwear", "nxp,k64f", "nxp,k6x";
+
+	aliases {
+		uart_0 = &uart0;
+		uart_4 = &uart4;
+		pinmux_a = &pinmux_a;
+		pinmux_b = &pinmux_b;
+		pinmux_c = &pinmux_c;
+		pinmux_d = &pinmux_d;
+		pinmux_e = &pinmux_e;
+		gpio_a = &gpioa;
+		gpio_b = &gpiob;
+		gpio_c = &gpioc;
+		gpio_d = &gpiod;
+		gpio_e = &gpioe;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+	};
+
+};
+
+&uart0 {
+	status = "ok";
+};
diff --git a/dts/arm/hexiwear_k64.fixup b/dts/arm/hexiwear_k64.fixup
new file mode 100644
index 00000000000..d62f7b7f0fa
--- /dev/null
+++ b/dts/arm/hexiwear_k64.fixup
@@ -0,0 +1,20 @@
+#define CONFIG_NUM_IRQS			ARM_ARMV7M_NVIC_E000E100_NUM_IRQS
+#define CONFIG_NUM_IRQ_PRIO_BITS	ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
+
+#define CONFIG_UART_MCUX_0_BAUD_RATE	NXP_UART_K64F_4006A000_BAUD_RATE
+#define CONFIG_UART_MCUX_0_IRQ_PRI	NXP_UART_K64F_4006A000_ZEPHYR_IRQ_PRIO
+
+#define CONFIG_UART_MCUX_1_BAUD_RATE	NXP_UART_K64F_4006B000_BAUD_RATE
+#define CONFIG_UART_MCUX_1_IRQ_PRI	NXP_UART_K64F_4006B000_ZEPHYR_IRQ_PRIO
+
+#define CONFIG_UART_MCUX_2_BAUD_RATE	NXP_UART_K64F_4006C000_BAUD_RATE
+#define CONFIG_UART_MCUX_2_IRQ_PRI	NXP_UART_K64F_4006C000_ZEPHYR_IRQ_PRIO
+
+#define CONFIG_UART_MCUX_3_BAUD_RATE	NXP_UART_K64F_4006D000_BAUD_RATE
+#define CONFIG_UART_MCUX_3_IRQ_PRI	NXP_UART_K64F_4006D000_ZEPHYR_IRQ_PRIO
+
+#define CONFIG_UART_MCUX_4_BAUD_RATE	NXP_UART_K64F_400EA000_BAUD_RATE
+#define CONFIG_UART_MCUX_4_IRQ_PRI	NXP_UART_K64F_400EA000_ZEPHYR_IRQ_PRIO
+
+#define CONFIG_UART_MCUX_5_BAUD_RATE	NXP_UART_K64F_400EB000_BAUD_RATE
+#define CONFIG_UART_MCUX_5_IRQ_PRI	NXP_UART_K64F_400EB000_ZEPHYR_IRQ_PRIO