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tests: drivers: dma test on stm32f7 requires nocache memory

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Config the sram0 to be non-cachable to PASS the DMA testcases
chan_blen_transfer and loop_transfer
on the stm32f746zg and stm32f767zi nucleo boards.

The CONFIG_NOCACHE_MEMORY is useless as the memory region
gets the NOCACHE ATTRibutes for stm32H7 or stm32F7 as well.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2023-12-20 10:49:20 +01:00 • committed by Carles Cufí
commit 82bace6e0d
10 changed files with 22 additions and 9 deletions
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1
tests/drivers/dma/loop_transfer/boards/nucleo_f746zg.conf
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@ -1,2 +1 @@
CONFIG_NOCACHE_MEMORY=y
CONFIG_DMA_LOOP_TRANSFER_CHANNEL_NR=0

5
tests/drivers/dma/loop_transfer/boards/nucleo_f746zg.overlay
View file

@ -5,3 +5,8 @@
*/
test_dma0: &dma2 { };
/* The test driver expects the SRAM0 region to be non-cachable */
&sram0 {
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
};

1
tests/drivers/dma/loop_transfer/boards/nucleo_f767zi.conf
View file

@ -1,2 +1 @@
CONFIG_NOCACHE_MEMORY=y
CONFIG_DMA_LOOP_TRANSFER_CHANNEL_NR=0

5
tests/drivers/dma/loop_transfer/boards/nucleo_f767zi.overlay
View file

@ -11,3 +11,8 @@
test_dma0: &dma2 {
status = "okay";
};
/* The test driver expects the SRAM0 region to be non-cachable */
&sram0 {
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
};

3
tests/drivers/dma/loop_transfer/boards/nucleo_h743zi.conf
View file

@ -6,6 +6,3 @@ CONFIG_DMA_LOOP_TRANSFER_NUMBER_OF_DMAS=2
# has access to this section.
CONFIG_CODE_DATA_RELOCATION=y
CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM4"
# Required for SRAM4 to be non-cachable
CONFIG_NOCACHE_MEMORY=y