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soc: riscv: litex-vexriscv: change CSR accessors

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Do not assume `reg_size` to be a multiple of 4 and
divide it on each call, expect the caller to provide
an already divided value instead.

This change require the LiteX GPIO driver to be modified,
which will come in the following commit.

Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
This commit is contained in:
Pawel Czarnecki 2020-05-11 12:32:04 +02:00 • committed by Carles Cufí
commit 82acea40b3
1 changed files with 12 additions and 14 deletions
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26
soc/riscv/litex-vexriscv/soc.h
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@ -10,6 +10,9 @@
#include "../riscv-privilege/common/soc_common.h" #include "../riscv-privilege/common/soc_common.h"
#include <devicetree.h> #include <devicetree.h>
#define LITEX_SUBREG_SIZE 0x1
#define LITEX_SUBREG_SIZE_BIT (LITEX_SUBREG_SIZE * 8)
/* lib-c hooks required RAM defined variables */ /* lib-c hooks required RAM defined variables */
#define RISCV_RAM_BASE DT_REG_ADDR(DT_INST(0, mmio_sram)) #define RISCV_RAM_BASE DT_REG_ADDR(DT_INST(0, mmio_sram))
#define RISCV_RAM_SIZE DT_REG_SIZE(DT_INST(0, mmio_sram)) #define RISCV_RAM_SIZE DT_REG_SIZE(DT_INST(0, mmio_sram))
@ -67,32 +70,27 @@ static inline void litex_write32(unsigned int value, unsigned long addr)
sys_write8(value, addr + 0xC); sys_write8(value, addr + 0xC);
} }
/* `reg_size` is assumed to be a multiple of 4 */
static inline void litex_write(volatile uint32_t *reg, uint32_t reg_size, uint32_t val) static inline void litex_write(volatile uint32_t *reg, uint32_t reg_size, uint32_t val)
{ {
uint32_t shifted_data; uint32_t shifted_data, i;
volatile uint32_t *reg_addr; volatile uint32_t *reg_addr;
uint32_t subregs = reg_size / 4;
for (int i = 0; i < subregs; ++i) { for (i = 0; i < reg_size; ++i) {
shifted_data = val >> ((subregs - i - 1) * 8); shifted_data = val >> ((reg_size - i - 1) *
LITEX_SUBREG_SIZE_BIT);
reg_addr = ((volatile uint32_t *) reg) + i; reg_addr = ((volatile uint32_t *) reg) + i;
*(reg_addr) = shifted_data; *(reg_addr) = shifted_data;
} }
} }
/* `reg_size` is assumed to be a multiple of 4 */
static inline uint32_t litex_read(volatile uint32_t *reg, uint32_t reg_size) static inline uint32_t litex_read(volatile uint32_t *reg, uint32_t reg_size)
{ {
uint32_t shifted_data; uint32_t shifted_data, i, result = 0;
volatile uint32_t *reg_addr;
uint32_t result = 0;
uint32_t subregs = reg_size / 4;
for (int i = 0; i < subregs; ++i) { for (i = 0; i < reg_size; ++i) {
reg_addr = ((volatile uint32_t *) reg) + i; shifted_data = *(reg + i) << ((reg_size - i - 1) *
shifted_data = *(reg_addr); LITEX_SUBREG_SIZE_BIT);
result |= (shifted_data << ((subregs - i - 1) * 8)); result |= shifted_data;
} }
return result; return result;