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drivers/interrupt_controller: Simplify IRTE structure for readability

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Let's avoid l/h accessors, and directly have all bits into one
structure.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2021-02-23 09:32:03 +01:00 • committed by Anas Nashif
commit 82961458de
2 changed files with 36 additions and 40 deletions
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24
drivers/interrupt_controller/intc_intel_vtd.c
View file

@ -83,7 +83,7 @@ static void vtd_flush_irte_from_cache(const struct device *dev,
if (!data->pwc) {
sys_cache_data_range(&data->irte[irte_idx],
sizeof(struct vtd_irte), K_CACHE_WB);
sizeof(union vtd_irte), K_CACHE_WB);
}
}
@ -320,24 +320,24 @@ static int vtd_ictl_remap(const struct device *dev,
uint32_t flags)
{
struct vtd_ictl_data *data = dev->data;
struct vtd_irte irte = { 0 };
union vtd_irte irte = { 0 };
irte.l.vector = vector;
irte.bits.vector = vector;
if (IS_ENABLED(CONFIG_X2APIC)) {
irte.l.dst_id = arch_curr_cpu()->id;
irte.bits.dst_id = arch_curr_cpu()->id;
} else {
irte.l.dst_id = arch_curr_cpu()->id << 8;
irte.bits.dst_id = arch_curr_cpu()->id << 8;
}
irte.l.trigger_mode = (flags & IOAPIC_TRIGGER_MASK) >> 15;
irte.l.delivery_mode = (flags & IOAPIC_DELIVERY_MODE_MASK) >> 8;
irte.l.dst_mode = 1;
irte.l.redirection_hint = 1;
irte.l.present = 1;
irte.bits.trigger_mode = (flags & IOAPIC_TRIGGER_MASK) >> 15;
irte.bits.delivery_mode = (flags & IOAPIC_DELIVERY_MODE_MASK) >> 8;
irte.bits.dst_mode = 1;
irte.bits.redirection_hint = 1;
irte.bits.present = 1;
data->irte[irte_idx].low = irte.low;
data->irte[irte_idx].high = irte.high;
data->irte[irte_idx].parts.low = irte.parts.low;
data->irte[irte_idx].parts.high = irte.parts.high;
vtd_index_iec_invalidate(dev, irte_idx);

24
drivers/interrupt_controller/intc_intel_vtd.h
View file

@ -16,9 +16,13 @@
((0x0FEE00000U) | (int_idx << 5) | shv | VTD_INT_FORMAT)
/* Interrupt Remapping Table Entry (IRTE) for Remapped Interrupts */
struct vtd_irte {
union {
struct vtd_irte_low {
union vtd_irte {
struct irte_parts {
uint64_t low;
uint64_t high;
} parts;
struct irte_bits {
uint64_t present : 1;
uint64_t fpd : 1;
uint64_t dst_mode : 1;
@ -31,20 +35,12 @@ struct vtd_irte {
uint64_t vector : 8;
uint64_t _reserved_1 : 8;
uint64_t dst_id : 32;
} l;
uint64_t low;
};
union {
struct vtd_irte_high {
uint64_t src_id : 16;
uint64_t src_id_qualifier : 2;
uint64_t src_validation_type : 2;
uint64_t _reserved : 44;
} h;
uint64_t high;
};
} __packed;
} bits __packed;
};
/* The table must be 4KB aligned, which is exactly 256 entries.
* And since we allow only 256 entries as a maximum: let's align to it.
@ -103,7 +99,7 @@ union qi_wait_descriptor {
#define QI_WAIT_STATUS_COMPLETE 0x1UL
struct vtd_ictl_data {
struct vtd_irte irte[IRTE_NUM] __aligned(0x1000);
union vtd_irte irte[IRTE_NUM] __aligned(0x1000);
struct qi_descriptor qi[QI_NUM] __aligned(0x1000);
int irqs[IRTE_NUM];
int vectors[IRTE_NUM];