From 82799d2ae429a53cccf24971e725d9e76d8f84f7 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Fri, 24 Jan 2020 12:04:01 +0100 Subject: [PATCH] dts: bindings: dma controller supports mem2mem transfer This checks if the DMA controller supports or not the memory-to-memory transfers. For DMA Version1, in the stm32f2xx, stm32f4xx, stm32f7xx series, only DMA instance 2 is able to transfer mem-to-mem. For other series, with DMA Version2, there is no such a limitation. Signed-off-by: Francois Ramu --- drivers/dma/dma_stm32.c | 2 ++ dts/arm/st/f0/stm32f0.dtsi | 1 - dts/arm/st/f1/stm32f1.dtsi | 1 - dts/arm/st/f3/stm32f3.dtsi | 1 - dts/arm/st/l0/stm32l0.dtsi | 1 - dts/arm/st/l4/stm32l4.dtsi | 2 -- dts/bindings/dma/st,stm32-dma.yaml | 2 +- 7 files changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/dma/dma_stm32.c b/drivers/dma/dma_stm32.c index 4747a60a9ad..abc15be4682 100644 --- a/drivers/dma/dma_stm32.c +++ b/drivers/dma/dma_stm32.c @@ -257,12 +257,14 @@ static int dma_stm32_configure(struct device *dev, u32_t id, return -EINVAL; } +#ifdef CONFIG_DMA_STM32_V1 if ((stream->direction == MEMORY_TO_MEMORY) && (!dev_config->support_m2m)) { LOG_ERR("Memcopy not supported for device %s", dev->config->name); return -ENOTSUP; } +#endif /* CONFIG_DMA_STM32_V1 */ if (config->source_data_size != 4U && config->source_data_size != 2U && diff --git a/dts/arm/st/f0/stm32f0.dtsi b/dts/arm/st/f0/stm32f0.dtsi index 11d0d2d09bd..1c06abee08a 100644 --- a/dts/arm/st/f0/stm32f0.dtsi +++ b/dts/arm/st/f0/stm32f0.dtsi @@ -317,7 +317,6 @@ reg = <0x40020000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; interrupts = <9 0 10 0 10 0 11 0 11 0>; - st,mem2mem; status = "disabled"; label = "DMA_1"; }; diff --git a/dts/arm/st/f1/stm32f1.dtsi b/dts/arm/st/f1/stm32f1.dtsi index 6b8ba40f87b..4e2957bc75a 100644 --- a/dts/arm/st/f1/stm32f1.dtsi +++ b/dts/arm/st/f1/stm32f1.dtsi @@ -265,7 +265,6 @@ reg = <0x40020000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; - st,mem2mem; status = "disabled"; label = "DMA_1"; }; diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi index 62a2d1c9b73..0c0ca7a0023 100644 --- a/dts/arm/st/f3/stm32f3.dtsi +++ b/dts/arm/st/f3/stm32f3.dtsi @@ -322,7 +322,6 @@ reg = <0x40020000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; - st,mem2mem; status = "disabled"; label = "DMA_1"; }; diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi index ab0b9544e14..5dfd2df21e7 100644 --- a/dts/arm/st/l0/stm32l0.dtsi +++ b/dts/arm/st/l0/stm32l0.dtsi @@ -186,7 +186,6 @@ reg = <0x40020000 0x400>; interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>; clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; - st,mem2mem; status = "disabled"; label = "DMA_1"; }; diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi index e4eb3f7725f..422007f10a1 100644 --- a/dts/arm/st/l4/stm32l4.dtsi +++ b/dts/arm/st/l4/stm32l4.dtsi @@ -316,7 +316,6 @@ reg = <0x40020000 0x400>; interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; - st,mem2mem; status = "disabled"; label = "DMA_1"; }; @@ -327,7 +326,6 @@ reg = <0x40020400 0x400>; interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>; clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>; - st,mem2mem; status = "disabled"; label = "DMA_2"; }; diff --git a/dts/bindings/dma/st,stm32-dma.yaml b/dts/bindings/dma/st,stm32-dma.yaml index 82da357339a..b014fb1baa0 100644 --- a/dts/bindings/dma/st,stm32-dma.yaml +++ b/dts/bindings/dma/st,stm32-dma.yaml @@ -16,7 +16,7 @@ properties: st,mem2mem: type: boolean - description: If the controller supports memory to memory transfer + description: If the DMA controller V1 supports memory to memory transfer "#dma-cells": const: 4