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arch: arm64: refactor for EL3 specific init

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Zephyr being an OS is typically expected to run at EL1. Arm core
can reset to EL3 which typically requires a firmware to run at EL3
and drop control to lower EL. In that case EL3 init is done by the
firmware allowing the lower EL software to have necessary control.

If Zephyr is entered at EL3 and it is desired to run at EL1, which
is indicated by 'CONFIG_SWITCH_TO_EL1', then Zephyr is responsible
for doing required EL3 initializations to allow lower EL necessary
control.

The entry sequence is modified to have control flow under single
'switch_el'.

Provisions added by giving weak funcions to do platform specific
init from EL3.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
This commit is contained in:
Sandeep Tripathy 2020-04-16 14:11:47 +05:30 • committed by Carles Cufí
commit 82724de6a5
2 changed files with 89 additions and 33 deletions
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23
include/arch/arm/aarch64/cpu.h
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@ -22,6 +22,12 @@
#define SPSR_MODE_EL1H (0x5)
#define SCTLR_EL3_RES1 (BIT(29) | BIT(28) | BIT(23) | \
BIT(22) | BIT(18) | BIT(16) | \
BIT(11) | BIT(5) | BIT(4))
#define SCTLR_EL1_RES1 (BIT(29) | BIT(28) | BIT(23) | \
BIT(22) | BIT(20) | BIT(11))
#define SCTLR_M_BIT BIT(0)
#define SCTLR_A_BIT BIT(1)
#define SCTLR_C_BIT BIT(2)
@ -36,6 +42,23 @@
#define SCR_EL3_EA BIT(3)
#define SCR_EL3_RW BIT(10)
/*
* TODO: ACTLR is of class implementation defined. All core implementations
* in armv8a have the same implementation so far w.r.t few controls.
* When there will be differences we have to create core specific headers.
*/
#define ACTLR_EL3_CPUACTLR BIT(0)
#define ACTLR_EL3_CPUECTLR BIT(1)
#define ACTLR_EL3_L2CTLR BIT(4)
#define ACTLR_EL3_L2ECTLR BIT(5)
#define ACTLR_EL3_L2ACTLR BIT(6)
#define CPTR_EL3_RES_VAL (0x0)
#define CPTR_EL3_EZ BIT(8)
#define CPTR_EL3_TFP BIT(9)
#define CPTR_EL3_TTA BIT(20)
#define CPTR_EL3_TCPAC BIT(31)
#define HCR_EL2_FMO BIT(3)
#define HCR_EL2_IMO BIT(4)
#define HCR_EL2_AMO BIT(5)