diff --git a/drivers/gpio/gpio_lpc11u6x.c b/drivers/gpio/gpio_lpc11u6x.c
index 11462a057c1..3b8ce39ab6c 100644
--- a/drivers/gpio/gpio_lpc11u6x.c
+++ b/drivers/gpio/gpio_lpc11u6x.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2020 Seagate Technology LLC
+ * Copyright 2022 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,9 +18,8 @@
 
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/gpio.h>
-#include <zephyr/drivers/pinmux.h>
 
-#include <zephyr/dt-bindings/pinctrl/lpc11u6x-pinctrl.h>
+#include <soc.h>
 
 #include "gpio_utils.h"
 
@@ -90,15 +90,14 @@ struct gpio_lpc11u6x_config {
 	/* gpio_driver_config needs to be first */
 	struct gpio_driver_config common;
 	const struct gpio_lpc11u6x_shared *shared;
-	char *pinmux_name;
 	uint8_t port_num;
 	uint8_t ngpios;
+	volatile uint32_t *iocon_base;
 };
 
 struct gpio_lpc11u6x_data {
 	/* gpio_driver_data needs to be first. */
 	struct gpio_driver_data common;
-	const struct device *pinmux_dev;
 	sys_slist_t cb_list;
 };
 
@@ -106,12 +105,11 @@ static int gpio_lpc11u6x_pin_configure(const struct device *port,
 				       gpio_pin_t pin, gpio_flags_t flags)
 {
 	const struct gpio_lpc11u6x_config *config = port->config;
-	struct gpio_lpc11u6x_data *data = port->data;
 	struct lpc11u6x_gpio_regs *gpio_regs = (struct lpc11u6x_gpio_regs *)
 		(config->shared->gpio_base + LPC11U6X_GPIO_REGS);
 	uint8_t port_num = config->port_num;
+	uint32_t offset;
 	uint32_t func;
-	int ret;
 
 	if (pin >= config->ngpios) {
 		return -EINVAL;
@@ -141,23 +139,27 @@ static int gpio_lpc11u6x_pin_configure(const struct device *port,
 	if (flags & GPIO_SINGLE_ENDED) {
 		/* Open source mode is not supported. */
 		if (flags & GPIO_LINE_OPEN_DRAIN)
-			func |= IOCON_OPENDRAIN_EN;
+			func |= IOCON_PIO_OD(1);
 		else
 			return -ENOTSUP;
 	}
 
 	if (flags & GPIO_PULL_UP) {
-		func |= IOCON_MODE_PULLUP;
+		func |= IOCON_PIO_MODE(0x2);
 	} else if (flags & GPIO_PULL_DOWN) {
-		func |= IOCON_MODE_PULLDOWN;
+		func |= IOCON_PIO_MODE(0x1);
 	} else {
-		func |= IOCON_MODE_INACT;
+		func |= IOCON_PIO_MODE(0x0);
 	}
 
-	ret = pinmux_pin_set(data->pinmux_dev, pin, func);
-	if (ret < 0) {
-		return ret;
+	/* Handle 4 bytes hole between PIO2_1 and PIO2_2. */
+	if (port_num == 2 && pin > 1) {
+		offset = pin + 1;
+	} else {
+		offset = pin;
 	}
+	/* iocon base + offset gives configuration register for this pin */
+	config->iocon_base[offset] = func;
 
 	/* Initial output value. */
 	if (flags & GPIO_OUTPUT_INIT_HIGH) {
@@ -511,17 +513,10 @@ do {							                \
 static int gpio_lpc11u6x_init(const struct device *dev)
 {
 	const struct gpio_lpc11u6x_config *config = dev->config;
-	struct gpio_lpc11u6x_data *data = dev->data;
 	const struct device *clock_dev;
 	int ret;
 	static bool gpio_ready;
 
-	/* Retrieve pinmux device. */
-	data->pinmux_dev = device_get_binding(config->pinmux_name);
-	if (!data->pinmux_dev) {
-		return -EINVAL;
-	}
-
 	/* Initialize shared resources only once. */
 	if (gpio_ready) {
 		return 0;
@@ -576,9 +571,9 @@ static const struct gpio_lpc11u6x_config				\
 	},								\
 	.shared = &gpio_lpc11u6x_shared,				\
 	.port_num = id,							\
-	.pinmux_name = DT_LABEL(DT_PHANDLE(DT_NODELABEL(gpio##id),	\
-				pinmux_port)),				\
 	.ngpios = DT_PROP(DT_NODELABEL(gpio##id), ngpios),		\
+	.iocon_base = (volatile uint32_t *)DT_REG_ADDR(			\
+		DT_INST_PHANDLE(id, iocon)),				\
 };									\
 									\
 static struct gpio_lpc11u6x_data gpio_lpc11u6x_data_##id;		\
diff --git a/dts/arm/nxp/nxp_lpc11u6x.dtsi b/dts/arm/nxp/nxp_lpc11u6x.dtsi
index 1d35e12daa8..24dbb8a67e9 100644
--- a/dts/arm/nxp/nxp_lpc11u6x.dtsi
+++ b/dts/arm/nxp/nxp_lpc11u6x.dtsi
@@ -118,7 +118,7 @@
 			ngpios = <24>;
 
 			clocks = <&syscon LPC11U6X_CLOCK_GPIO>;
-			pinmux-port = <&pinmux0>;
+			iocon = <&pio0>;
 
 			status = "disabled";
 		};
@@ -135,7 +135,7 @@
 			#gpio-cells = <2>;
 
 			clocks = <&syscon LPC11U6X_CLOCK_GPIO>;
-			pinmux-port = <&pinmux1>;
+			iocon = <&pio1>;
 
 			status = "disabled";
 		};
@@ -154,7 +154,7 @@
 			ngpios = <22>;
 
 			clocks = <&syscon LPC11U6X_CLOCK_GPIO>;
-			pinmux-port = <&pinmux2>;
+			iocon = <&pio2>;
 
 			status = "disabled";
 		};
diff --git a/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml b/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml
index a6f8ff32823..b99cc516917 100644
--- a/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml
+++ b/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml
@@ -29,12 +29,12 @@ properties:
     clocks:
       required: true
 
-    pinmux-port:
+    iocon:
       required: true
       type: phandle
       description: |
-        a phandle reference to the device tree node that contains the pinmux
-        port associated with this GPIO controller.
+        a phandle reference to the devicetree node that contains the pinmux
+        controller associated with the GPIO controller.
 
 gpio-cells:
   - pin