soc: renesas: Add initial support for RA4E2 soc
Initial commit to support Renesas RA4E2 SoC Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
This commit is contained in:
Quy Tran
Anas Nashif
parent
9ea4cb96cd
commit
81b83902cf
10 changed files with 564 additions and 0 deletions
169
dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
Normal file
169
dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
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@ -0,0 +1,169 @@
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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#include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
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/ {
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(40)>;
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};
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ioport8: gpio@40080100 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080100 0x20>;
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port = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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flash-controller@407e0000 {
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reg = <0x407e0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x0 DT_SIZE_K(128)>;
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};
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};
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id_code: id_code@100a120 {
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compatible = "zephyr,memory-region";
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reg = <0x0100a120 0x10>;
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zephyr,memory-region = "ID_CODE";
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status = "okay";
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};
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};
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clocks: clocks {
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xtal: clock-xtal {
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compatible = "renesas,ra-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pll: pll {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL */
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source = <RA_PLL_SOURCE_MAIN_OSC>;
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div = <RA_PLL_DIV_1>;
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mul = <10 0>;
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freq = <DT_FREQ_M(200)>;
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status = "disabled";
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};
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pclkblock: pclkblock {
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compatible = "renesas,ra-cgc-pclk-block";
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#clock-cells = <0>;
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sysclock-src = <RA_CLOCK_SOURCE_PLL>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclka: pclka {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkc: pclkc {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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fclk: fclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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clkout: clkout {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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uclk: uclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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canfdclk: canfdclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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i3cclk: i3cclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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cecclk: cecclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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};
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};
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};
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165
dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi
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165
dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi
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@ -0,0 +1,165 @@
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
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#include <freq.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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soc {
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interrupt-parent = <&nvic>;
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system: system@4001e000 {
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compatible = "renesas,ra-system";
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reg = <0x4001e000 0x1000>;
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status = "okay";
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};
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flash-controller@407e0000 {
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reg = <0x407e0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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ioport0: gpio@40080000 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080000 0x20>;
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port = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport1: gpio@40080020 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080020 0x20>;
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port = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport2: gpio@40080040 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080040 0x20>;
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port = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport3: gpio@40080060 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080060 0x20>;
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port = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport4: gpio@40080080 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080080 0x20>;
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port = <4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport5: gpio@400800a0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400800a0 0x20>;
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port = <5>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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pinctrl: pin-controller@40080800 {
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compatible = "renesas,ra-pinctrl-pfs";
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reg = <0x40080800 0x3c0>;
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status = "okay";
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};
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sci0: sci0@40118000 {
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compatible = "renesas,ra-sci";
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interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118000 0x100>;
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clocks = <&pclka MSTPB 31>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <0>;
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status = "disabled";
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};
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};
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sci9: sci9@40118900 {
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compatible = "renesas,ra-sci";
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interrupts = <36 1>, <37 1>, <38 1>, <39 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118900 0x100>;
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clocks = <&pclka MSTPB 22>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <9>;
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status = "disabled";
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};
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};
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option_setting_ofs: option_setting_ofs@100a100 {
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compatible = "zephyr,memory-region";
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reg = <0x0100a100 0x18>;
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zephyr,memory-region = "OPTION_SETTING_OFS";
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status = "okay";
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};
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option_setting_sas: option_setting_sas@100a134 {
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compatible = "zephyr,memory-region";
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reg = <0x0100a134 0xcc>;
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zephyr,memory-region = "OPTION_SETTING_SAS";
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status = "okay";
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};
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option_setting_s: option_setting_s@100a200 {
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compatible = "zephyr,memory-region";
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reg = <0x0100a200 0x100>;
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zephyr,memory-region = "OPTION_SETTING_S";
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status = "okay";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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12
soc/renesas/ra/ra4e2/CMakeLists.txt
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12
soc/renesas/ra/ra4e2/CMakeLists.txt
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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14
soc/renesas/ra/ra4e2/Kconfig
Normal file
14
soc/renesas/ra/ra4e2/Kconfig
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA4E2
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select ARM
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select CPU_HAS_ARM_MPU
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select CPU_CORTEX_M33
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select HAS_RENESAS_RA_FSP
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select CPU_CORTEX_M_HAS_DWT
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select ARMV8_M_DSP
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select CPU_HAS_FPU
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select FPU
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select HAS_SWO
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select XIP
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12
soc/renesas/ra/ra4e2/Kconfig.defconfig
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12
soc/renesas/ra/ra4e2/Kconfig.defconfig
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RA4E2
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config NUM_IRQS
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default 96
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config PINCTRL
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default y
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endif # SOC_SERIES_RA4E2
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20
soc/renesas/ra/ra4e2/Kconfig.soc
Normal file
20
soc/renesas/ra/ra4e2/Kconfig.soc
Normal file
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA4E2
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bool
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select SOC_FAMILY_RENESAS_RA
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help
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Renesas RA4E2 series
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config SOC_R7FA4E2B93CFM
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bool
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select SOC_SERIES_RA4E2
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help
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R7FA4E2B93CFM
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config SOC_SERIES
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default "ra4e2" if SOC_SERIES_RA4E2
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config SOC
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default "r7fa4e2b93cfm" if SOC_R7FA4E2B93CFM
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84
soc/renesas/ra/ra4e2/sections.ld
Normal file
84
soc/renesas/ra/ra4e2/sections.ld
Normal file
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.code_in_ram :
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{
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. = ALIGN(4);
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__Code_In_RAM_Start = .;
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KEEP(*(.code_in_ram*))
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__Code_In_RAM_End = .;
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} > RAMABLE_REGION
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SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
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{
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/* If DTC is used, put the DTC vector table at the start of SRAM.
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This avoids memory holes due to 1K alignment required by it. */
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*(.fsp_dtc_vector_table)
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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SECTION_PROLOGUE(.option_setting_ofs,,)
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{
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__OPTION_SETTING_OFS_Start = .;
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KEEP(*(.option_setting_ofs0))
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. = __OPTION_SETTING_OFS_Start + 0x04;
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KEEP(*(.option_setting_ofs2))
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. = __OPTION_SETTING_OFS_Start + 0x10;
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KEEP(*(.option_setting_dualsel))
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__OPTION_SETTING_OFS_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
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SECTION_PROLOGUE(.option_setting_sas,,)
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{
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__OPTION_SETTING_SAS_Start = .;
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KEEP(*(.option_setting_sas))
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__OPTION_SETTING_SAS_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
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SECTION_PROLOGUE(.option_setting_s,,)
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{
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__OPTION_SETTING_S_Start = .;
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KEEP(*(.option_setting_ofs1_sec))
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. = __OPTION_SETTING_S_Start + 0x04;
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KEEP(*(.option_setting_ofs3_sec))
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. = __OPTION_SETTING_S_Start + 0x10;
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KEEP(*(.option_setting_banksel_sec))
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. = __OPTION_SETTING_S_Start + 0x40;
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KEEP(*(.option_setting_bps_sec0))
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. = __OPTION_SETTING_S_Start + 0x44;
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KEEP(*(.option_setting_bps_sec1))
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. = __OPTION_SETTING_S_Start + 0x48;
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KEEP(*(.option_setting_bps_sec2))
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. = __OPTION_SETTING_S_Start + 0x4C;
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KEEP(*(.option_setting_bps_sec3))
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. = __OPTION_SETTING_S_Start + 0x60;
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KEEP(*(.option_setting_pbps_sec0))
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. = __OPTION_SETTING_S_Start + 0x64;
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KEEP(*(.option_setting_pbps_sec1))
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. = __OPTION_SETTING_S_Start + 0x68;
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KEEP(*(.option_setting_pbps_sec2))
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. = __OPTION_SETTING_S_Start + 0x6C;
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KEEP(*(.option_setting_pbps_sec3))
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. = __OPTION_SETTING_S_Start + 0x80;
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KEEP(*(.option_setting_ofs1_sel))
|
||||
. = __OPTION_SETTING_S_Start + 0x84;
|
||||
KEEP(*(.option_setting_ofs3_sel))
|
||||
. = __OPTION_SETTING_S_Start + 0x90;
|
||||
KEEP(*(.option_setting_banksel_sel))
|
||||
. = __OPTION_SETTING_S_Start + 0xC0;
|
||||
KEEP(*(.option_setting_bps_sel0))
|
||||
. = __OPTION_SETTING_S_Start + 0xC4;
|
||||
KEEP(*(.option_setting_bps_sel1))
|
||||
. = __OPTION_SETTING_S_Start + 0xC8;
|
||||
KEEP(*(.option_setting_bps_sel2))
|
||||
. = __OPTION_SETTING_S_Start + 0xCC;
|
||||
KEEP(*(.option_setting_bps_sel3))
|
||||
__OPTION_SETTING_S_End = .;
|
||||
} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
|
||||
|
||||
SECTION_PROLOGUE(.id_code,,)
|
||||
{
|
||||
KEEP(*(.id_code*))
|
||||
} GROUP_LINK_IN(ID_CODE)
|
||||
69
soc/renesas/ra/ra4e2/soc.c
Normal file
69
soc/renesas/ra/ra4e2/soc.c
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief System/hardware module for Renesas RA4E2 family processor
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/arch/cpu.h>
|
||||
#include <cmsis_core.h>
|
||||
#include <zephyr/arch/arm/nmi.h>
|
||||
#include <zephyr/irq.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
#include "bsp_cfg.h"
|
||||
#include <bsp_api.h>
|
||||
|
||||
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
|
||||
|
||||
volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
|
||||
|
||||
/**
|
||||
* @brief Perform basic hardware initialization at boot.
|
||||
*
|
||||
* This needs to be run from the very beginning.
|
||||
* So the init priority has to be 0 (zero).
|
||||
*
|
||||
* @return 0
|
||||
*/
|
||||
static int renesas_ra4e2_init(void)
|
||||
{
|
||||
extern volatile uint16_t g_protect_counters[];
|
||||
for (uint32_t i = 0; i < 4; i++) {
|
||||
g_protect_counters[i] = 0;
|
||||
}
|
||||
|
||||
#if FSP_PRIV_TZ_USE_SECURE_REGS
|
||||
/* Disable protection using PRCR register. */
|
||||
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
|
||||
|
||||
/* Initialize peripherals to secure mode for flat projects */
|
||||
R_PSCU->PSARB = 0;
|
||||
R_PSCU->PSARC = 0;
|
||||
R_PSCU->PSARD = 0;
|
||||
R_PSCU->PSARE = 0;
|
||||
|
||||
R_CPSCU->ICUSARG = 0;
|
||||
R_CPSCU->ICUSARH = 0;
|
||||
R_CPSCU->ICUSARI = 0;
|
||||
|
||||
/* Enable protection using PRCR register. */
|
||||
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
|
||||
#endif
|
||||
|
||||
SystemCoreClock = BSP_MOCO_HZ;
|
||||
g_protect_pfswe_counter = 0;
|
||||
bsp_clock_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(renesas_ra4e2_init, PRE_KERNEL_1, 0);
|
||||
16
soc/renesas/ra/ra4e2/soc.h
Normal file
16
soc/renesas/ra/ra4e2/soc.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the Renesas RA4E2 family MCU
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_RENESAS_RA4E2_SOC_H_
|
||||
#define ZEPHYR_SOC_RENESAS_RA4E2_SOC_H_
|
||||
|
||||
#include <bsp_api.h>
|
||||
|
||||
#endif /* ZEPHYR_SOC_RENESAS_RA4_SOC_H_ */
|
||||
|
|
@ -4,6 +4,9 @@ family:
|
|||
- name: ra2a1
|
||||
socs:
|
||||
- name: r7fa2a1ab3cfm
|
||||
- name: ra4e2
|
||||
socs:
|
||||
- name: r7fa4e2b93cfm
|
||||
- name: ra4m1
|
||||
socs:
|
||||
- name: r7fa4m1ab3cfm
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue