soc: renesas: Add initial support for RA4E2 soc

Initial commit to support Renesas RA4E2 SoC

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>

dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi

@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
+
+/ {
+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(40)>;
+		};
+
+		ioport8: gpio@40080100 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40080100 0x20>;
+			port = <8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		flash-controller@407e0000 {
+			reg = <0x407e0000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0x0 DT_SIZE_K(128)>;
+			};
+		};
+
+		id_code: id_code@100a120 {
+			compatible = "zephyr,memory-region";
+			reg = <0x0100a120 0x10>;
+			zephyr,memory-region = "ID_CODE";
+			status = "okay";
+		};
+	};
+
+	clocks: clocks {
+		xtal: clock-xtal {
+			compatible = "renesas,ra-cgc-external-clock";
+			clock-frequency = <DT_FREQ_M(20)>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		hoco: clock-hoco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(20)>;
+			#clock-cells = <0>;
+		};
+
+		moco: clock-moco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+		};
+
+		loco: clock-loco {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		subclk: clock-subclk {
+			compatible = "renesas,ra-cgc-subclk";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			compatible = "renesas,ra-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL */
+			source = <RA_PLL_SOURCE_MAIN_OSC>;
+			div = <RA_PLL_DIV_1>;
+			mul = <10 0>;
+			freq = <DT_FREQ_M(200)>;
+			status = "disabled";
+		};
+
+		pclkblock: pclkblock {
+			compatible = "renesas,ra-cgc-pclk-block";
+			#clock-cells = <0>;
+			sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+			status = "okay";
+
+			iclk: iclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclka: pclka {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkb: pclkb {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkc: pclkc {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkd: pclkd {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			fclk: fclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			clkout: clkout {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			uclk: uclk {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			canfdclk: canfdclk {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			i3cclk: i3cclk {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			cecclk: cecclk {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+		};
+	};
+};

dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi

@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
+#include <freq.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m33";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	soc {
+		interrupt-parent = <&nvic>;
+
+		system: system@4001e000 {
+			compatible = "renesas,ra-system";
+			reg = <0x4001e000 0x1000>;
+			status = "okay";
+		};
+
+		flash-controller@407e0000 {
+			reg = <0x407e0000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		ioport0: gpio@40080000 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40080000 0x20>;
+			port = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport1: gpio@40080020 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40080020 0x20>;
+			port = <1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport2: gpio@40080040 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40080040 0x20>;
+			port = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport3: gpio@40080060 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40080060 0x20>;
+			port = <3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport4: gpio@40080080 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40080080 0x20>;
+			port = <4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport5: gpio@400800a0 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x400800a0 0x20>;
+			port = <5>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		pinctrl: pin-controller@40080800 {
+			compatible = "renesas,ra-pinctrl-pfs";
+			reg = <0x40080800 0x3c0>;
+			status = "okay";
+		};
+
+		sci0: sci0@40118000 {
+			compatible = "renesas,ra-sci";
+			interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40118000 0x100>;
+			clocks = <&pclka MSTPB 31>;
+			status = "disabled";
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <0>;
+				status = "disabled";
+			};
+		};
+
+		sci9: sci9@40118900 {
+			compatible = "renesas,ra-sci";
+			interrupts = <36 1>, <37 1>, <38 1>, <39 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40118900 0x100>;
+			clocks = <&pclka MSTPB 22>;
+			status = "disabled";
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <9>;
+				status = "disabled";
+			};
+		};
+
+		option_setting_ofs: option_setting_ofs@100a100 {
+			compatible = "zephyr,memory-region";
+			reg = <0x0100a100 0x18>;
+			zephyr,memory-region = "OPTION_SETTING_OFS";
+			status = "okay";
+		};
+
+		option_setting_sas: option_setting_sas@100a134 {
+			compatible = "zephyr,memory-region";
+			reg = <0x0100a134 0xcc>;
+			zephyr,memory-region = "OPTION_SETTING_SAS";
+			status = "okay";
+		};
+
+		option_setting_s: option_setting_s@100a200 {
+			compatible = "zephyr,memory-region";
+			reg = <0x0100a200 0x100>;
+			zephyr,memory-region = "OPTION_SETTING_S";
+			status = "okay";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};

soc/renesas/ra/ra4e2/CMakeLists.txt

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/ra/ra4e2/Kconfig

@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA4E2
+	select ARM
+	select CPU_HAS_ARM_MPU
+	select CPU_CORTEX_M33
+	select HAS_RENESAS_RA_FSP
+	select CPU_CORTEX_M_HAS_DWT
+	select ARMV8_M_DSP
+	select CPU_HAS_FPU
+	select FPU
+	select HAS_SWO
+	select XIP

soc/renesas/ra/ra4e2/Kconfig.defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA4E2
+
+config NUM_IRQS
+	default 96
+
+config PINCTRL
+	default y
+
+endif # SOC_SERIES_RA4E2

soc/renesas/ra/ra4e2/Kconfig.soc

@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA4E2
+	bool
+	select SOC_FAMILY_RENESAS_RA
+	help
+	  Renesas RA4E2 series
+
+config SOC_R7FA4E2B93CFM
+	bool
+	select SOC_SERIES_RA4E2
+	help
+	  R7FA4E2B93CFM
+
+config SOC_SERIES
+	default "ra4e2" if SOC_SERIES_RA4E2
+
+config SOC
+	default "r7fa4e2b93cfm" if SOC_R7FA4E2B93CFM

soc/renesas/ra/ra4e2/sections.ld

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+	. = ALIGN(4);
+	__Code_In_RAM_Start = .;
+	KEEP(*(.code_in_ram*))
+	__Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+	/* If DTC is used, put the DTC vector table at the start of SRAM.
+		This avoids memory holes due to 1K alignment required by it. */
+	*(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+	__OPTION_SETTING_OFS_Start = .;
+	KEEP(*(.option_setting_ofs0))
+	. = __OPTION_SETTING_OFS_Start + 0x04;
+	KEEP(*(.option_setting_ofs2))
+	. = __OPTION_SETTING_OFS_Start + 0x10;
+	KEEP(*(.option_setting_dualsel))
+	__OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+	__OPTION_SETTING_SAS_Start = .;
+	KEEP(*(.option_setting_sas))
+	__OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+	__OPTION_SETTING_S_Start = .;
+	KEEP(*(.option_setting_ofs1_sec))
+	. = __OPTION_SETTING_S_Start + 0x04;
+	KEEP(*(.option_setting_ofs3_sec))
+	. = __OPTION_SETTING_S_Start + 0x10;
+	KEEP(*(.option_setting_banksel_sec))
+	. = __OPTION_SETTING_S_Start + 0x40;
+	KEEP(*(.option_setting_bps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x44;
+	KEEP(*(.option_setting_bps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x48;
+	KEEP(*(.option_setting_bps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x4C;
+	KEEP(*(.option_setting_bps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x60;
+	KEEP(*(.option_setting_pbps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x64;
+	KEEP(*(.option_setting_pbps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x68;
+	KEEP(*(.option_setting_pbps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x6C;
+	KEEP(*(.option_setting_pbps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x80;
+	KEEP(*(.option_setting_ofs1_sel))
+	. = __OPTION_SETTING_S_Start + 0x84;
+	KEEP(*(.option_setting_ofs3_sel))
+	. = __OPTION_SETTING_S_Start + 0x90;
+	KEEP(*(.option_setting_banksel_sel))
+	. = __OPTION_SETTING_S_Start + 0xC0;
+	KEEP(*(.option_setting_bps_sel0))
+	. = __OPTION_SETTING_S_Start + 0xC4;
+	KEEP(*(.option_setting_bps_sel1))
+	. = __OPTION_SETTING_S_Start + 0xC8;
+	KEEP(*(.option_setting_bps_sel2))
+	. = __OPTION_SETTING_S_Start + 0xCC;
+	KEEP(*(.option_setting_bps_sel3))
+	__OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+SECTION_PROLOGUE(.id_code,,)
+{
+    KEEP(*(.id_code*))
+} GROUP_LINK_IN(ID_CODE)

soc/renesas/ra/ra4e2/soc.c

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA4E2 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/arch/arm/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra4e2_init(void)
+{
+	extern volatile uint16_t g_protect_counters[];
+	for (uint32_t i = 0; i < 4; i++) {
+		g_protect_counters[i] = 0;
+	}
+
+#if FSP_PRIV_TZ_USE_SECURE_REGS
+	/* Disable protection using PRCR register. */
+	R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+
+	/* Initialize peripherals to secure mode for flat projects */
+	R_PSCU->PSARB = 0;
+	R_PSCU->PSARC = 0;
+	R_PSCU->PSARD = 0;
+	R_PSCU->PSARE = 0;
+
+	R_CPSCU->ICUSARG = 0;
+	R_CPSCU->ICUSARH = 0;
+	R_CPSCU->ICUSARI = 0;
+
+	/* Enable protection using PRCR register. */
+	R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
+#endif
+
+	SystemCoreClock = BSP_MOCO_HZ;
+	g_protect_pfswe_counter = 0;
+	bsp_clock_init();
+
+	return 0;
+}
+
+SYS_INIT(renesas_ra4e2_init, PRE_KERNEL_1, 0);

soc/renesas/ra/ra4e2/soc.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA4E2 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA4E2_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA4E2_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA4_SOC_H_ */

soc/renesas/ra/soc.yml

@@ -4,6 +4,9 @@ family:
       - name: ra2a1
         socs:
           - name: r7fa2a1ab3cfm
+      - name: ra4e2
+        socs:
+          - name: r7fa4e2b93cfm
       - name: ra4m1
         socs:
           - name: r7fa4m1ab3cfm