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drivers: dma_mcux_edma: add support dma driver for s32k344

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On S32K344, the offset in memory map between each channel
is 0x4000 for most channels, but there is specific case is
between channel 11 and 12 which is 0x1D4000 instead. As a
consequence, 32 channels are divided to two parts: one
starts from channel 0 -> 11. The other is from channel 128
to 145. The channel gap is from 12 -> 127.

For user and data structures in shim driver, the channel's
value comes from 0 --> 31. Above constraint will be counted
when interact with the mcux sdk

Beside that, the DMAMUX register in this platform is very
specific, not in identical with DMAMUX channel, so shim
driver is updated to cover this case

Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This commit is contained in:
Dat Nguyen Duy 2023-06-14 10:23:06 +07:00 • committed by David Leach
commit 8185faa0cb
5 changed files with 121 additions and 23 deletions
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soc/arm/nxp_s32/s32k/Kconfig.series
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@ -19,5 +19,6 @@ config SOC_SERIES_S32K3_M7
select HAS_MCUX_FLEXCAN
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
select HAS_MCUX_CACHE
help
Enable support for NXP S32K3 MCUs family on Cortex-M7 cores