tests: drivers: clock_control: stm32 common: also test get_status
Add clock_control_get_status checks to the stm32_common_devices adc and i2c tests, to verify that checking the status of gating clocks and domain clock sources works. Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
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2 changed files with 35 additions and 2 deletions
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@ -54,13 +54,24 @@ ZTEST(stm32_common_devices_clocks, test_adc_clk_config)
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uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
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uint32_t dev_actual_clk_src;
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int r;
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enum clock_control_status status;
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status = clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t)&pclken[0]);
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zassert_true((status == CLOCK_CONTROL_STATUS_OFF),
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"ADC1 gating clock should be off initially");
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/* Test clock_on(gating clock) */
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r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0]);
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zassert_true((r == 0), "Could not enable ADC1 gating clock");
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zassert_true(ADC_IS_CLK_ENABLED(), "ADC1 gating clock should be on");
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/* Check via HAL as well as via get_status API */
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zassert_true(ADC_IS_CLK_ENABLED(), "[HAL] ADC1 gating clock should be on");
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status = clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t)&pclken[0]);
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zassert_true((status == CLOCK_CONTROL_STATUS_ON),
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"[Zephyr] ADC1 gating clock should be on");
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TC_PRINT("ADC1 gating clock on\n");
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if (IS_ENABLED(STM32_ADC_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(adc1)) > 1) {
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@ -87,6 +98,11 @@ ZTEST(stm32_common_devices_clocks, test_adc_clk_config)
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zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src);
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}
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/* Test status of the used clk source */
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status = clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t)&pclken[1]);
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zassert_true((status == CLOCK_CONTROL_STATUS_ON), "ADC1 clk src must to be on");
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/* Test get_rate(srce clk) */
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r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[1],
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@ -28,6 +28,7 @@
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static void i2c_set_clock(const struct stm32_pclken *clk)
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{
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uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
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enum clock_control_status status;
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/* Test clock_on(domain_clk) */
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int r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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@ -51,6 +52,11 @@ static void i2c_set_clock(const struct stm32_pclken *clk)
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zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src);
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}
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/* Test status of the used clk source */
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status = clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t)clk);
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zassert_true((status == CLOCK_CONTROL_STATUS_ON), "I2C1 clk src must to be on");
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/* Test get_rate(srce clk) */
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r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) clk,
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@ -71,13 +77,24 @@ ZTEST(stm32_common_devices_clocks, test_i2c_clk_config)
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uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
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int r;
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enum clock_control_status status;
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status = clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t)&pclken[0]);
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zassert_true((status == CLOCK_CONTROL_STATUS_OFF),
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"I2C Gating clock should be off initially");
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/* Test clock_on(gating clock) */
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r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0]);
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zassert_true((r == 0), "Could not enable I2C gating clock");
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zassert_true(__HAL_RCC_I2C1_IS_CLK_ENABLED(), "I2C1 gating clock should be on");
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/* Check via HAL as well as via get_status API */
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zassert_true(__HAL_RCC_I2C1_IS_CLK_ENABLED(), "[HAL] I2C1 gating clock should be on");
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status = clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t)&pclken[0]);
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zassert_true((status == CLOCK_CONTROL_STATUS_ON),
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"[Zephyr] I2C1 gating clock should be on");
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TC_PRINT("I2C1 gating clock on\n");
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if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) > 1) {
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