diff --git a/boards/st/stm32u5g9j_dk2/board.cmake b/boards/st/stm32u5g9j_dk2/board.cmake
index 2bce8d8fc43..55f2baf523d 100644
--- a/boards/st/stm32u5g9j_dk2/board.cmake
+++ b/boards/st/stm32u5g9j_dk2/board.cmake
@@ -3,6 +3,9 @@
 
 # keep first
 board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+if(CONFIG_STM32_MEMMAP)
+board_runner_args(stm32cubeprogrammer "--extload=MX66LM1G45G_STM32U5G9J-DK2.stldr")
+endif()
 
 board_runner_args(openocd "--tcl-port=6666")
 board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable")
diff --git a/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts b/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts
index 351e9030bff..2e09189fcd7 100644
--- a/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts
+++ b/boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts
@@ -58,6 +58,14 @@
 		volt-sensor0 = &vref1;
 		volt-sensor1 = &vbat4;
 	};
+
+	ext_memory: memory@a0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xa0000000 DT_SIZE_M(128)>;
+		zephyr,memory-region = "EXTMEM";
+		/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
+	};
 };
 
 &ltdc {
@@ -319,9 +327,45 @@ zephyr_udc0: &usbotg_hs {
 	};
 };
 
+&xspi1 {
+	clocks = <&rcc STM32_CLOCK(AHB2_2, 12U)>,
+			 <&rcc STM32_SRC_PLL2_Q HSPI_SEL(2)>;
+
+	pinctrl-0 = <&hspi1_dqs0_pi2 &hspi1_ncs_ph9
+		&hspi1_io0_ph10 &hspi1_io1_ph11
+		&hspi1_io2_ph12 &hspi1_io3_ph13
+		&hspi1_io4_ph14 &hspi1_io5_ph15
+		&hspi1_io6_pi0 &hspi1_io7_pi1
+		&hspi1_clk_pi3>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	mx66lm1g45: xspi-nor-flash@0 {
+		compatible = "st,stm32-xspi-nor";
+		reg = <0>;
+		size = <DT_SIZE_M(1024)>; /* 1 Gbits */
+		ospi-max-frequency = <DT_FREQ_M(133)>;
+		spi-bus-width = <XSPI_OCTO_MODE>;
+		data-rate = <XSPI_DTR_TRANSFER>;
+		four-byte-opcodes;
+		status = "okay";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			extflash_partition: partition@0 {
+				label = "ext_storage";
+				reg = <0 DT_SIZE_M(128)>;
+			};
+		};
+	};
+};
+
 &rtc {
 	clocks =  <&rcc STM32_CLOCK_BUS_APB3 0x00200000>,
-			<&rcc STM32_SRC_LSE RTC_SEL(1)>;
+			  <&rcc STM32_SRC_LSE RTC_SEL(1)>;
 	status = "okay";
 };