michaelh/zephyr
1
0
Fork 0
Code Releases Activity

boards: arm: arty: add arm cortex-m3 designstart fpga board definition

Browse source 
Add board definition for the ARM Cortex-M3 DesignStart FPGA reference
design running on the Digilent Arty development board.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit is contained in:
Henrik Brix Andersen 2020-08-27 20:12:40 +02:00 • committed by Ioannis Glaropoulos
commit 80cb465a89
8 changed files with 154 additions and 22 deletions
Download patch file Download diff file Expand all files Collapse all files

4
boards/arm/arty/Kconfig.board
View file

@ -6,3 +6,7 @@
config BOARD_ARTY_A7_ARM_DESIGNSTART_M1
bool "Digilent Arty A7 ARM DesignStart Cortex-M1"
depends on SOC_SERIES_ARM_DESIGNSTART
config BOARD_ARTY_A7_ARM_DESIGNSTART_M3
bool "Digilent Arty A7 ARM DesignStart Cortex-M3"
depends on SOC_SERIES_ARM_DESIGNSTART

10
boards/arm/arty/Kconfig.defconfig
View file

@ -3,14 +3,18 @@
# Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
# SPDX-License-Identifier: Apache-2.0
if BOARD_ARTY_A7_ARM_DESIGNSTART_M1
if BOARD_ARTY_A7_ARM_DESIGNSTART_M1 || BOARD_ARTY_A7_ARM_DESIGNSTART_M3
config BOARD
default "arty_a7_arm_designstart_m1"
default "arty_a7_arm_designstart_m1" if BOARD_ARTY_A7_ARM_DESIGNSTART_M1
default "arty_a7_arm_designstart_m3" if BOARD_ARTY_A7_ARM_DESIGNSTART_M3
config CPU_CORTEX_M_HAS_SYSTICK
default y
config CPU_HAS_ARM_MPU
default y if BOARD_ARTY_A7_ARM_DESIGNSTART_M3
config NUM_IRQS
default 8
@ -42,4 +46,4 @@ config SPI_NOR
endif # FLASH
endif # BOARD_ARTY_A7_ARM_DESIGNSTART_M1
endif # BOARD_ARTY_A7_ARM_DESIGNSTART_M1 || BOARD_ARTY_A7_ARM_DESIGNSTART_M3

53
boards/arm/arty/arty_a7_arm_designstart_m3.dts Normal file
View file

@ -0,0 +1,53 @@
/*
* Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/armv7-m.dtsi>
#include "arty_a7_arm_designstart.dtsi"
/ {
model = "Digilent Arty A7 ARM DesignStart Cortex-M3";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m3";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv7m-mpu";
reg = <0xe000ed90 0x40>;
arm,num-mpu-regions = <8>;
};
};
};
soc {
itcm: memory@0 {
compatible = "arm,itcm";
reg = <0x00000000 DT_SIZE_K(32)>;
};
dtcm: memory@20000000 {
compatible = "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(32)>;
};
bram0: memory@60000000 {
compatible = "mmio-sram";
reg = <0x60000000 DT_SIZE_K(8)>;
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};

13
boards/arm/arty/arty_a7_arm_designstart_m3.yaml Normal file
View file

@ -0,0 +1,13 @@
identifier: arty_a7_arm_designstart_m3
name: Digilent Arty A7 ARM DesignStart Cortex-M3
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32
flash: 32
supported:
- flash
- spi

13
boards/arm/arty/arty_a7_arm_designstart_m3_defconfig Normal file
View file

@ -0,0 +1,13 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_SOC_SERIES_ARM_DESIGNSTART=y
CONFIG_SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3=y
CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M3=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=50000000
CONFIG_ARM_MPU=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

6
boards/arm/arty/board.cmake
View file

@ -4,6 +4,12 @@ if(CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M1)
board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m1.cfg")
board_runner_args(jlink "--device=Cortex-M1" "--reset-after-load")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
elseif(CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M3)
board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m3.cfg")
board_runner_args(jlink "--device=Cortex-M3" "--reset-after-load")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
endif()

66
boards/arm/arty/doc/index.rst
View file

@ -25,15 +25,18 @@ The Spartan-7 and Artix-7 based Arty board do not contain a CPU, but require a
so-called soft processor to be instantiated within the FPGA in order to run
Zephyr. The Zynq-7000 based Arty boards are not yet supported by Zephyr.
ARM Cortex-M1 DesignStart FPGA
******************************
ARM Cortex-M1/M3 DesignStart FPGA
*********************************
One such soft processor design is the Cortex-M1 `ARM DesignStart FPGA`_ Xilinx
edition reference design from ARM. This design targets the Spartan-7 or Artix-7
based Arty boards. Zephyr only supports the Artix-7 based boards for now.
One way of instantiating soft processors on the Arty is using the `ARM
DesignStart FPGA`_ Xilinx edition reference designs from ARM. Zephyr supports
both the Cortex-M1 and the Cortex-M3 reference designs. The Cortex-M1 design
targets either the Spartan-7 or Artix-7 based Arty boards, whereas the Cortex-M3
design only targets the Artix-7 based boards. Zephyr only supports the Artix-7
targetted designs for now.
For more information about the ARM Cortex-M1 DesignStart FPGA, see the following
websites:
For more information about the ARM Cortex-M1/M3 DesignStart FPGA, see the
following websites:
- `Technical Resources for DesignStart FPGA`_
- `Technical Resources for DesignStart FPGA on Xilinx`_
@ -43,7 +46,7 @@ Supported Features
==================
The ``arty_a7_arm_designstart_m1`` board configuration supports the following
hardware features:
hardware features of the Cortex-M1 reference design:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
@ -60,15 +63,29 @@ hardware features:
| QSPI | on-chip | QSPI flash |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:file:`boards/arm/arty/arty_a7_arm_designstart_m1_defconfig`. Other hardware
features are not currently supported by the port.
The default configuration for the Cortex-M1 can be found in the defconfig file:
:file:`boards/arm/arty/arty_a7_arm_designstart_m1_defconfig`.
In addition to the above, the ``arty_a7_arm_designstart_m3`` board configuration
supports the following hardware features of the Cortex-M3 reference design:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| MPU | on-chip | Memory Protection Unit |
+-----------+------------+-------------------------------------+
The default configuration for the Cortex-M3 can be found in the defconfig file:
:file:`boards/arm/arty/arty_a7_arm_designstart_m3_defconfig`.
Other hardware features are not currently supported by the port.
System Clock
============
The reference design is configured to use the 100 MHz external oscillator on the
board as CPU system clock.
The Cortex-M1 reference design is configured to use the 100 MHz external
oscillator on the board as CPU system clock whereas the Cortex-M3 reference
design is configured for 50MHz CPU system clock.
Serial Port
===========
@ -93,10 +110,10 @@ The external SWD debug probe can be connected to connector ``J4`` (``nSRST`` on
Programming and Debugging
*************************
First, configure the FPGA with the reference design FPGA bitstream using Xilinx
Vivado as described in the ARM Cortex-M1 DesignStart FPGA Xilinx edition user
guide (available as part of the reference design download from `Technical
Resources for DesignStart FPGA on Xilinx`_).
First, configure the FPGA with the selected reference design FPGA bitstream
using Xilinx Vivado as described in the ARM Cortex-M1/Cortex-M3 DesignStart FPGA
Xilinx edition user guide (available as part of the reference design download
from `Technical Resources for DesignStart FPGA on Xilinx`_).
Another option for configuring the FPGA with the reference design bitstream is
to use the :ref:`openocd-debug-host-tools`:
@ -107,6 +124,14 @@ to use the :ref:`openocd-debug-host-tools`:
pld load 0 m1_for_arty_a7_reference.bit;\
shutdown"
or:
.. code-block:: console
openocd -f board/arty_s7.cfg -c "init;\
pld load 0 m3_for_arty_a7_reference.bit;\
shutdown"
Next, build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
@ -128,7 +153,8 @@ etc.):
Flashing
========
Here is an example for the :ref:`hello_world` application.
Here is an example for building and flashing the :ref:`hello_world` application
for the Cortex-M1 reference design:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
@ -142,13 +168,15 @@ After flashing, you should see message similar to the following in the terminal:
*** Booting Zephyr OS build zephyr-v2.3.99 ***
Hello World! arty_a7_arm_designstart_m1
The same procedure can be used for the Cortex-M3 reference design.
Note, however, that the application was not persisted in flash memory by the
above steps. It was merely written to internal block RAM in the FPGA. It will
revert to the application stored in the block RAM within the FPGA bitstream
the next time the FPGA is configured.
The steps to persist the application within the FPGA bitstream are covered by
the ARM Cortex-M1 DesignStart FPGA Xilinx edition user guide. If the
the ARM Cortex-M1/M3 DesignStart FPGA Xilinx edition user guide. If the
:option:`CONFIG_BUILD_OUTPUT_BIN` is enabled and the `SiFive elf2hex`_ package
is available, the build system will automatically generate a Verilog memory hex
dump :file:`zephyr.mem` file suitable for initialising the block RAM using

11
boards/arm/arty/support/openocd_arty_a7_arm_designstart_m3.cfg Normal file
View file

@ -0,0 +1,11 @@
source [find interface/cmsis-dap.cfg]
source [find target/swj-dp.tcl]
adapter_khz 5000
set _CHIPNAME cortex_m3
set _ENDIAN little
set _WORKAREASIZE 0x4000
set _CPUTAPID 0x412FC231
source [find openocd_arty_a7_arm_designstart.cfg]