From 8048b141359ca816fcd342aefdda7baa8ff08b2c Mon Sep 17 00:00:00 2001 From: Evgeniy Paltsev Date: Wed, 7 Apr 2021 19:23:23 +0300 Subject: [PATCH] ARC: allow to build code for processors without ZOL ARCv3 64 bit processors doesn't have Zero Delay Loop (also named Zero Overhead Loop, ZOL) mechanism. Add kconfig option to remove ZOL register save/restore so the code can be build for both ARCv2 and ARCv3. Signed-off-by: Eugeniy Paltsev Signed-off-by: Evgeniy Paltsev --- arch/arc/Kconfig | 12 ++++++++++++ arch/arc/core/fatal.c | 2 ++ arch/arc/core/offsets/offsets.c | 2 ++ arch/arc/core/regular_irq.S | 2 ++ arch/arc/include/kernel_arch_data.h | 4 ++++ arch/arc/include/swap_macros.h | 4 ++++ arch/arc/include/v2/irq.h | 2 ++ 7 files changed, 28 insertions(+) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 0bb64d3660e..80d02bd6826 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -104,6 +104,18 @@ config FP_FPU_DA menu "ARC CPU Options" +config ARC_HAS_ZOL + bool + depends on ISA_ARCV2 + default y + help + ARCv2 CPUs have ZOL hardware loop mechanism which the ARCv3 ISA drops. + Architecturally ZOL provides + - LPcc instruction + - LP_COUNT core reg + - LP_START, LP_END aux regs + Disabling this option removes usage of ZOL regs from code + config NUM_IRQ_PRIO_LEVELS int "Number of supported interrupt priority levels" range 1 16 diff --git a/arch/arc/core/fatal.c b/arch/arc/core/fatal.c index 7f5037dbef0..829f71a09bc 100644 --- a/arch/arc/core/fatal.c +++ b/arch/arc/core/fatal.c @@ -33,8 +33,10 @@ static void dump_arc_esf(const z_arch_esf_t *esf) LOG_ERR("r12: 0x%" PRIxPTR " r13: 0x%" PRIxPTR " pc: 0x%" PRIxPTR "", esf->r12, esf->r13, esf->pc); LOG_ERR(" blink: 0x%" PRIxPTR " status32: 0x%" PRIxPTR "", esf->blink, esf->status32); +#ifdef CONFIG_ARC_HAS_ZOL LOG_ERR("lp_end: 0x%" PRIxPTR " lp_start: 0x%" PRIxPTR " lp_count: 0x%" PRIxPTR "", esf->lp_end, esf->lp_start, esf->lp_count); +#endif /* CONFIG_ARC_HAS_ZOL */ } #endif diff --git a/arch/arc/core/offsets/offsets.c b/arch/arc/core/offsets/offsets.c index 23736f93362..07222bef612 100644 --- a/arch/arc/core/offsets/offsets.c +++ b/arch/arc/core/offsets/offsets.c @@ -58,9 +58,11 @@ GEN_OFFSET_SYM(_isf_t, r11); GEN_OFFSET_SYM(_isf_t, r12); GEN_OFFSET_SYM(_isf_t, r13); GEN_OFFSET_SYM(_isf_t, blink); +#ifdef CONFIG_ARC_HAS_ZOL GEN_OFFSET_SYM(_isf_t, lp_end); GEN_OFFSET_SYM(_isf_t, lp_start); GEN_OFFSET_SYM(_isf_t, lp_count); +#endif /* CONFIG_ARC_HAS_ZOL */ #ifdef CONFIG_CODE_DENSITY GEN_OFFSET_SYM(_isf_t, ei_base); GEN_OFFSET_SYM(_isf_t, ldi_base); diff --git a/arch/arc/core/regular_irq.S b/arch/arc/core/regular_irq.S index c8d2ad1bd63..1008594d374 100644 --- a/arch/arc/core/regular_irq.S +++ b/arch/arc/core/regular_irq.S @@ -300,8 +300,10 @@ _rirq_switch_from_coop: SUBR sp, sp, ___isf_t_pc_OFFSET +#ifdef CONFIG_ARC_HAS_ZOL /* reset zero-overhead loops */ STR 0, sp, ___isf_t_lp_end_OFFSET +#endif /* CONFIG_ARC_HAS_ZOL */ /* * r13 is part of both the callee and caller-saved register sets because diff --git a/arch/arc/include/kernel_arch_data.h b/arch/arc/include/kernel_arch_data.h index 3c0c39d7e96..94c5f9f126e 100644 --- a/arch/arc/include/kernel_arch_data.h +++ b/arch/arc/include/kernel_arch_data.h @@ -37,9 +37,11 @@ extern "C" { #ifdef CONFIG_ARC_HAS_SECURE struct _irq_stack_frame { +#ifdef CONFIG_ARC_HAS_ZOL uintptr_t lp_end; uintptr_t lp_start; uintptr_t lp_count; +#endif /* CONFIG_ARC_HAS_ZOL */ #ifdef CONFIG_CODE_DENSITY /* * Currently unsupported. This is where those registers are @@ -86,9 +88,11 @@ struct _irq_stack_frame { uintptr_t r12; uintptr_t r13; uintptr_t blink; +#ifdef CONFIG_ARC_HAS_ZOL uintptr_t lp_end; uintptr_t lp_start; uintptr_t lp_count; +#endif /* CONFIG_ARC_HAS_ZOL */ #ifdef CONFIG_CODE_DENSITY /* * Currently unsupported. This is where those registers are diff --git a/arch/arc/include/swap_macros.h b/arch/arc/include/swap_macros.h index 451458528a1..558e5948448 100644 --- a/arch/arc/include/swap_macros.h +++ b/arch/arc/include/swap_macros.h @@ -196,12 +196,14 @@ STR r1, sp, ___isf_t_r1_OFFSET STR r0, sp, ___isf_t_r0_OFFSET +#ifdef CONFIG_ARC_HAS_ZOL MOVR r0, lp_count STR r0, sp, ___isf_t_lp_count_OFFSET LRR r1, [_ARC_V2_LP_START] LRR r0, [_ARC_V2_LP_END] STR r1, sp, ___isf_t_lp_start_OFFSET STR r0, sp, ___isf_t_lp_end_OFFSET +#endif /* CONFIG_ARC_HAS_ZOL */ #ifdef CONFIG_CODE_DENSITY lr r1, [_ARC_V2_JLI_BASE] @@ -231,12 +233,14 @@ sr r2, [_ARC_V2_EI_BASE] #endif +#ifdef CONFIG_ARC_HAS_ZOL LDR r0, sp, ___isf_t_lp_count_OFFSET MOVR lp_count, r0 LDR r1, sp, ___isf_t_lp_start_OFFSET LDR r0, sp, ___isf_t_lp_end_OFFSET SRR r1, [_ARC_V2_LP_START] SRR r0, [_ARC_V2_LP_END] +#endif /* CONFIG_ARC_HAS_ZOL */ LDR r13, sp, ___isf_t_r13_OFFSET LDR r12, sp, ___isf_t_r12_OFFSET diff --git a/arch/arc/include/v2/irq.h b/arch/arc/include/v2/irq.h index 1f2a1a63deb..4bdd20be74c 100644 --- a/arch/arc/include/v2/irq.h +++ b/arch/arc/include/v2/irq.h @@ -54,7 +54,9 @@ extern "C" { static ALWAYS_INLINE void z_irq_setup(void) { uint32_t aux_irq_ctrl_value = ( +#ifdef CONFIG_ARC_HAS_ZOL _ARC_V2_AUX_IRQ_CTRL_LOOP_REGS | /* save lp_xxx registers */ +#endif /* CONFIG_ARC_HAS_ZOL */ #ifdef CONFIG_CODE_DENSITY _ARC_V2_AUX_IRQ_CTRL_LP | /* save code density registers */ #endif