boards: nordic: 54L: Refactor the board DT
Refactor the 54L board file to be able to better support out-of-tree non-secure boards. This aligns better with nrf53's DT. Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
This commit is contained in:
Sebastian Bøe
Anas Nashif
parent
90332b9a0b
commit
80209e4fd0
2 changed files with 152 additions and 137 deletions
150
boards/nordic/nrf54l15pdk/nrf54l15_cpuapp_common.dtsi
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150
boards/nordic/nrf54l15pdk/nrf54l15_cpuapp_common.dtsi
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* This file is common to the secure and non-secure domain */
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#include <nordic/nrf54l15_cpuapp.dtsi>
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#include "nrf54l15pdk_nrf54l15-common.dtsi"
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/ {
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chosen {
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zephyr,console = &uart20;
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zephyr,shell-uart = &uart20;
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zephyr,uart-mcumgr = &uart20;
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zephyr,flash-controller = &rram_controller;
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zephyr,flash = &cpuapp_rram;
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zephyr,ieee802154 = &ieee802154;
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};
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aliases {
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spi-flash0 = &mx25r64;
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};
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};
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&cpuapp_sram {
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status = "okay";
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};
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&lfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <15500>;
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};
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&hfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <15000>;
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};
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&grtc {
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owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
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/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
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child-owned-channels = <3 4 7 8 9 10 11>;
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status = "okay";
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};
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&cpuapp_rram {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x10000 DT_SIZE_K(324)>;
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};
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slot0_ns_partition: partition@61000 {
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label = "image-0-nonsecure";
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reg = <0x61000 DT_SIZE_K(324)>;
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};
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slot1_partition: partition@b2000 {
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label = "image-1";
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reg = <0xb2000 DT_SIZE_K(324)>;
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};
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slot1_ns_partition: partition@103000 {
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label = "image-1-nonsecure";
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reg = <0x103000 DT_SIZE_K(324)>;
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};
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/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
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storage_partition: partition@15c000 {
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label = "storage";
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reg = <0x15c000 DT_SIZE_K(36)>;
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};
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};
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};
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&uart20 {
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status = "okay";
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hw-flow-control;
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpiote20 {
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status = "okay";
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};
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&gpiote30 {
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status = "okay";
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};
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&radio {
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status = "okay";
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};
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&ieee802154 {
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status = "okay";
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};
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&temp {
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status = "okay";
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};
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&clock {
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status = "okay";
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};
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&spi00 {
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status = "okay";
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cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&spi00_default>;
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pinctrl-1 = <&spi00_sleep>;
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pinctrl-names = "default", "sleep";
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mx25r64: mx25r6435f@0 {
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compatible = "jedec,spi-nor";
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status = "disabled";
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reg = <0>;
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spi-max-frequency = <8000000>;
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jedec-id = [c2 28 17];
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sfdp-bfp = [
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e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
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ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
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10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44
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30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
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];
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size = <67108864>;
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has-dpd;
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t-enter-dpd = <10000>;
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t-exit-dpd = <35000>;
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};
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};
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&adc {
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status = "okay";
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};
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@ -5,150 +5,15 @@
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*/
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/dts-v1/;
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#include <nordic/nrf54l15_cpuapp.dtsi>
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#include "nrf54l15pdk_nrf54l15-common.dtsi"
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#include "nrf54l15_cpuapp_common.dtsi"
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/ {
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compatible = "nordic,nrf54l15pdk_nrf54l15-cpuapp";
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model = "Nordic nRF54L15 PDK nRF54L15 Application MCU";
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chosen {
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zephyr,console = &uart20;
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zephyr,shell-uart = &uart20;
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zephyr,uart-mcumgr = &uart20;
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zephyr,flash-controller = &rram_controller;
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zephyr,flash = &cpuapp_rram;
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zephyr,code-partition = &slot0_partition;
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zephyr,sram = &cpuapp_sram;
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zephyr,ieee802154 = &ieee802154;
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};
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aliases {
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spi-flash0 = &mx25r64;
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};
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};
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&cpuapp_sram {
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status = "okay";
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};
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&lfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <15500>;
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};
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&hfxo {
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load-capacitors = "internal";
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load-capacitance-femtofarad = <15000>;
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};
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&grtc {
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owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
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/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
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child-owned-channels = <3 4 7 8 9 10 11>;
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status = "okay";
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};
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&cpuapp_rram {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x10000 DT_SIZE_K(324)>;
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};
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slot0_ns_partition: partition@61000 {
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label = "image-0-nonsecure";
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reg = <0x61000 DT_SIZE_K(324)>;
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};
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slot1_partition: partition@b2000 {
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label = "image-1";
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reg = <0xb2000 DT_SIZE_K(324)>;
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};
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slot1_ns_partition: partition@103000 {
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label = "image-1-nonsecure";
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reg = <0x103000 DT_SIZE_K(324)>;
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};
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/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
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storage_partition: partition@15c000 {
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label = "storage";
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reg = <0x15c000 DT_SIZE_K(36)>;
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};
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};
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};
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&uart20 {
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status = "okay";
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hw-flow-control;
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpiote20 {
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status = "okay";
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};
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&gpiote30 {
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status = "okay";
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};
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&radio {
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status = "okay";
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};
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&ieee802154 {
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status = "okay";
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};
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&temp {
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status = "okay";
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};
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&clock {
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status = "okay";
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};
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&spi00 {
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status = "okay";
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cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&spi00_default>;
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pinctrl-1 = <&spi00_sleep>;
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pinctrl-names = "default", "sleep";
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mx25r64: mx25r6435f@0 {
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compatible = "jedec,spi-nor";
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status = "disabled";
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reg = <0>;
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spi-max-frequency = <8000000>;
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jedec-id = [c2 28 17];
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sfdp-bfp = [
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e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
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ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
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10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44
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30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
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];
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size = <67108864>;
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has-dpd;
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t-enter-dpd = <10000>;
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t-exit-dpd = <35000>;
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};
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};
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&adc {
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status = "okay";
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};
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