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boards: arm: mimxrt1050_evk: added support for hyperflash

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This is all the settings for the hyperflash driver in the dts.

Signed-off-by: Nicolai Glud <nicolai.glud@prevas.dk>
This commit is contained in:
Nicolai Glud 2021-09-20 13:03:57 +02:00 • committed by David Leach
commit 8012228e71
4 changed files with 85 additions and 1 deletions
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3
boards/arm/mimxrt1050_evk/Kconfig.defconfig
View file

@ -6,7 +6,8 @@
if BOARD_MIMXRT1050_EVK || BOARD_MIMXRT1050_EVK_QSPI if BOARD_MIMXRT1050_EVK || BOARD_MIMXRT1050_EVK_QSPI
config BOARD config BOARD
default "mimxrt1050_evk" default "mimxrt1050_evk" if BOARD_MIMXRT1050_EVK
default "mimxrt1050_evk_qspi" if BOARD_MIMXRT1050_EVK_QSPI
choice CODE_LOCATION choice CODE_LOCATION
default CODE_FLEXSPI default CODE_FLEXSPI

47
boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts
View file

@ -25,6 +25,9 @@
zephyr,dtcm = &dtcm; zephyr,dtcm = &dtcm;
zephyr,console = &lpuart1; zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1; zephyr,shell-uart = &lpuart1;
zephyr,flash-controller = &s26ks512s0;
zephyr,flash = &s26ks512s0;
zephyr,code-partition = &slot0_partition;
}; };
sdram0: memory@80000000 { sdram0: memory@80000000 {
@ -91,6 +94,14 @@
arduino_serial: &lpuart3 {}; arduino_serial: &lpuart3 {};
&flexspi { &flexspi {
status = "okay";
ahb-prefetch;
ahb-read-addr-opt;
ahb-bufferable;
ahb-cacheable;
sck-differential-clock;
combination-mode;
rx-clock-source = <3>;
reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>;
s26ks512s0: s26ks512s@0 { s26ks512s0: s26ks512s@0 {
compatible = "nxp,imx-flexspi-hyperflash"; compatible = "nxp,imx-flexspi-hyperflash";
@ -98,7 +109,43 @@ arduino_serial: &lpuart3 {};
label = "S26KS512S"; label = "S26KS512S";
reg = <0>; reg = <0>;
spi-max-frequency = <166000000>; spi-max-frequency = <166000000>;
word-addressable;
cs-interval-unit = <1>;
cs-interval = <2>;
cs-hold-time = <0>;
cs-setup-time = <3>;
data-valid-time = <1>;
column-space = <3>;
ahb-write-wait-unit = <2>;
ahb-write-wait-interval = <20>;
status = "okay"; status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(256)>;
};
slot0_partition: partition@40000 {
label = "image-0";
reg = <0x00040000 DT_SIZE_M(3)>;
};
slot1_partition: partition@340000 {
label = "image-1";
reg = <0x00340000 DT_SIZE_M(3)>;
};
scratch_partition: partition@640000 {
label = "image-scratch";
reg = <0x00640000 DT_SIZE_K(768)>;
};
storage_partition: partition@700000 {
label = "storage";
reg = <0x00700000 DT_SIZE_M(57)>;
};
};
}; };
}; };

8
boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.dts
View file

@ -8,6 +8,14 @@
/delete-node/ &s26ks512s0; /delete-node/ &s26ks512s0;
/ {
chosen {
/delete-property/ zephyr,flash-controller;
/delete-property/ zephyr,flash;
/delete-property/ zephyr,code-partition;
};
};
&flexspi { &flexspi {
reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
is25wp064: is25wp064@0 { is25wp064: is25wp064@0 {

28
boards/arm/mimxrt1050_evk/pinmux.c
View file

@ -344,6 +344,34 @@ static int mimxrt1050_evk_init(const struct device *dev)
GPIO_PinInit(GPIO2, 31, &config); GPIO_PinInit(GPIO2, 31, &config);
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay) && CONFIG_FLASH_MCUX_FLEXSPI_HYPERFLASH
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0x0130F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0x10F1U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
mimxrt1050_evk_usdhc_pinmux(0, true, 2, 1); mimxrt1050_evk_usdhc_pinmux(0, true, 2, 1);
imxrt_usdhc_pinmux_cb_register(mimxrt1050_evk_usdhc_pinmux); imxrt_usdhc_pinmux_cb_register(mimxrt1050_evk_usdhc_pinmux);