aarch64: mmu: cleanups and fixes
Major changes: - move related functions together - optimize add_map() not to walk the page tables *twice* on every loop - properly handle leftover size when a range is already mapped - don't overwrite existing mappings by default - return an error when the mapping fails and make the code clearer overall. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre
Anas Nashif
parent
dfd8e7522d
commit
7fcf5519d0
3 changed files with 179 additions and 152 deletions
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@ -8,6 +8,8 @@
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#include <device.h>
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#include <init.h>
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#include <kernel.h>
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#include <kernel_arch_interface.h>
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#include <logging/log.h>
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#include <arch/arm/aarch64/cpu.h>
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#include <arch/arm/aarch64/arm_mmu.h>
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#include <linker/linker-defs.h>
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@ -15,6 +17,8 @@
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#include "arm_mmu.h"
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LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
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static uint64_t kernel_xlat_tables[CONFIG_MAX_XLAT_TABLES * Ln_XLAT_NUM_ENTRIES]
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__aligned(Ln_XLAT_NUM_ENTRIES * sizeof(uint64_t));
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@ -22,75 +26,16 @@ static struct arm_mmu_ptables kernel_ptables = {
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.xlat_tables = kernel_xlat_tables,
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};
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/* Translation table control register settings */
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static uint64_t get_tcr(int el)
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/* Returns a new preallocated table */
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static uint64_t *new_prealloc_table(struct arm_mmu_ptables *ptables)
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{
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uint64_t tcr;
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uint64_t va_bits = CONFIG_ARM64_VA_BITS;
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uint64_t tcr_ps_bits;
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ptables->next_table++;
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tcr_ps_bits = TCR_PS_BITS;
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if (el == 1) {
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tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
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/*
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* TCR_EL1.EPD1: Disable translation table walk for addresses
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* that are translated using TTBR1_EL1.
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*/
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tcr |= TCR_EPD1_DISABLE;
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} else
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tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT);
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tcr |= TCR_T0SZ(va_bits);
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/*
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* Translation table walk is cacheable, inner/outer WBWA and
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* inner shareable
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*/
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tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
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return tcr;
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}
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static int pte_desc_type(uint64_t *pte)
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{
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return *pte & PTE_DESC_TYPE_MASK;
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}
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static uint64_t *calculate_pte_index(struct arm_mmu_ptables *ptables,
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uintptr_t addr, unsigned int level)
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{
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int base_level = BASE_XLAT_LEVEL;
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uint64_t *pte;
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uint64_t idx;
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unsigned int i;
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/* Walk through all translation tables to find pte index */
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pte = (uint64_t *)ptables->xlat_tables;
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for (i = base_level; i < XLAT_LEVEL_MAX; i++) {
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idx = XLAT_TABLE_VA_IDX(addr, i);
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pte += idx;
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/* Found pte index */
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if (i == level)
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return pte;
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/* if PTE is not table desc, can't traverse */
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if (pte_desc_type(pte) != PTE_TABLE_DESC)
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return NULL;
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/* Move to the next translation table level */
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pte = (uint64_t *)(*pte & 0x0000fffffffff000ULL);
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if (ptables->next_table >= CONFIG_MAX_XLAT_TABLES) {
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LOG_ERR("CONFIG_MAX_XLAT_TABLES, too small");
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return NULL;
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}
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return NULL;
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}
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static void set_pte_table_desc(uint64_t *pte, uint64_t *table, unsigned int level)
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{
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#if DUMP_PTE
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MMU_DEBUG("%s", XLAT_TABLE_LEVEL_SPACE(level));
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MMU_DEBUG("%p: [Table] %p\n", pte, table);
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#endif
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/* Point pte to new table */
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*pte = PTE_TABLE_DESC | (uint64_t)table;
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return &ptables->xlat_tables[ptables->next_table * Ln_XLAT_NUM_ENTRIES];
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}
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static uint64_t get_region_desc(uint32_t attrs)
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@ -159,16 +104,50 @@ static uint64_t get_region_desc(uint32_t attrs)
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return desc;
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}
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static uint64_t get_region_desc_from_pte(uint64_t *pte)
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static inline bool is_free_desc(uint64_t desc)
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{
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return ((*pte) & DESC_ATTRS_MASK);
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return (desc & PTE_DESC_TYPE_MASK) == PTE_INVALID_DESC;
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}
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static void set_pte_block_desc(uint64_t *pte, uint64_t addr_pa,
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uint64_t desc, unsigned int level)
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static inline bool is_table_desc(uint64_t desc, unsigned int level)
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{
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desc |= addr_pa;
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desc |= (level == 3) ? PTE_PAGE_DESC : PTE_BLOCK_DESC;
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return level != XLAT_LAST_LEVEL &&
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(desc & PTE_DESC_TYPE_MASK) == PTE_TABLE_DESC;
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}
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static inline bool is_block_desc(uint64_t desc)
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{
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return (desc & PTE_DESC_TYPE_MASK) == PTE_BLOCK_DESC;
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}
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static inline uint64_t *pte_desc_table(uint64_t desc)
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{
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uint64_t address = desc & GENMASK(47, PAGE_SIZE_SHIFT);
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return (uint64_t *)address;
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}
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static inline bool is_desc_superset(uint64_t desc1, uint64_t desc2,
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unsigned int level)
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{
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uint64_t mask = DESC_ATTRS_MASK | GENMASK(47, LEVEL_TO_VA_SIZE_SHIFT(level));
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return (desc1 & mask) == (desc2 & mask);
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}
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static void set_pte_table_desc(uint64_t *pte, uint64_t *table, unsigned int level)
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{
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#if DUMP_PTE
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MMU_DEBUG("%s", XLAT_TABLE_LEVEL_SPACE(level));
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MMU_DEBUG("%p: [Table] %p\n", pte, table);
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#endif
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/* Point pte to new table */
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*pte = PTE_TABLE_DESC | (uint64_t)table;
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}
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static void set_pte_block_desc(uint64_t *pte, uint64_t desc, unsigned int level)
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{
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desc |= (level == XLAT_LAST_LEVEL) ? PTE_PAGE_DESC : PTE_BLOCK_DESC;
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#if DUMP_PTE
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uint8_t mem_type = (desc >> 2) & MT_TYPE_MASK;
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@ -188,97 +167,105 @@ static void set_pte_block_desc(uint64_t *pte, uint64_t addr_pa,
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*pte = desc;
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}
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/* Returns a new reallocated table */
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static uint64_t *new_prealloc_table(struct arm_mmu_ptables *ptables)
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static void populate_table(uint64_t *table, uint64_t desc, unsigned int level)
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{
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ptables->next_table++;
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unsigned int stride_shift = LEVEL_TO_VA_SIZE_SHIFT(level);
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unsigned int i;
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__ASSERT(ptables->next_table < CONFIG_MAX_XLAT_TABLES,
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"Enough xlat tables not allocated");
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MMU_DEBUG("Populating table with PTE 0x%016llx(L%d)\n", desc, level);
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return (uint64_t *)(&ptables->xlat_tables[ptables->next_table *
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Ln_XLAT_NUM_ENTRIES]);
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}
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/* Splits a block into table with entries spanning the old block */
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static void split_pte_block_desc(struct arm_mmu_ptables *ptables, uint64_t *pte,
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uint64_t desc, unsigned int level)
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{
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uint64_t old_block_desc = *pte;
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uint64_t *new_table;
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unsigned int i = 0;
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/* get address size shift bits for next level */
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unsigned int levelshift = LEVEL_TO_VA_SIZE_SHIFT(level + 1);
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MMU_DEBUG("Splitting existing PTE %p(L%d)\n", pte, level);
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new_table = new_prealloc_table(ptables);
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for (i = 0; i < Ln_XLAT_NUM_ENTRIES; i++) {
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new_table[i] = old_block_desc | (i << levelshift);
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if ((level + 1) == 3)
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new_table[i] |= PTE_PAGE_DESC;
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if (level == XLAT_LAST_LEVEL) {
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desc |= PTE_PAGE_DESC;
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}
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/* Overwrite existing PTE set the new table into effect */
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set_pte_table_desc(pte, new_table, level);
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for (i = 0; i < Ln_XLAT_NUM_ENTRIES; i++) {
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table[i] = desc | (i << stride_shift);
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}
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}
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static void add_map(struct arm_mmu_ptables *ptables, const char *name,
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uintptr_t phys, uintptr_t virt, size_t size, uint32_t attrs)
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static int add_map(struct arm_mmu_ptables *ptables, const char *name,
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uintptr_t phys, uintptr_t virt, size_t size, uint32_t attrs)
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{
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uint64_t desc, *pte;
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uint64_t level_size;
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uint64_t *new_table;
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uint64_t *table = ptables->xlat_tables;
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unsigned int level = BASE_XLAT_LEVEL;
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MMU_DEBUG("mmap [%s]: virt %lx phys %lx size %lx\n",
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name, virt, phys, size);
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/* check minimum alignment requirement for given mmap region */
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__ASSERT(((virt & (CONFIG_MMU_PAGE_SIZE - 1)) == 0) &&
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((size & (CONFIG_MMU_PAGE_SIZE - 1)) == 0),
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__ASSERT(((virt | phys | size) & (CONFIG_MMU_PAGE_SIZE - 1)) == 0,
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"address/size are not page aligned\n");
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desc = get_region_desc(attrs);
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desc = phys | get_region_desc(attrs);
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while (size) {
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__ASSERT(level < XLAT_LEVEL_MAX,
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__ASSERT(level <= XLAT_LAST_LEVEL,
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"max translation table level exceeded\n");
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/* Locate PTE for given virtual address and page table level */
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pte = calculate_pte_index(ptables, virt, level);
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__ASSERT(pte != NULL, "pte not found\n");
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pte = &table[XLAT_TABLE_VA_IDX(virt, level)];
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if (is_table_desc(*pte, level)) {
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/* Move to the next translation table level */
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level++;
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table = pte_desc_table(*pte);
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continue;
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}
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if (!(attrs & MT_OVERWRITE) && !is_free_desc(*pte)) {
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/* the entry is already allocated */
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LOG_ERR("entry already in use: "
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"level %d pte %p *pte 0x%016llx",
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level, pte, *pte);
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return -EBUSY;
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}
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level_size = 1ULL << LEVEL_TO_VA_SIZE_SHIFT(level);
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if (size >= level_size && !(virt & (level_size - 1))) {
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/* Given range fits into level size,
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* create block/page descriptor
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*/
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set_pte_block_desc(pte, phys, desc, level);
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virt += level_size;
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phys += level_size;
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size -= level_size;
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/* Range is mapped, start again for next range */
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level = BASE_XLAT_LEVEL;
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} else if (pte_desc_type(pte) == PTE_INVALID_DESC) {
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/* Range doesn't fit, create subtable */
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new_table = new_prealloc_table(ptables);
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set_pte_table_desc(pte, new_table, level);
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level++;
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} else if (pte_desc_type(pte) == PTE_BLOCK_DESC) {
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/* Check if the block is already mapped with the correct attrs */
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if (desc == get_region_desc_from_pte(pte))
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return;
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if (is_desc_superset(*pte, desc, level)) {
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/* This block already covers our range */
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level_size -= (virt & (level_size - 1));
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if (level_size > size) {
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level_size = size;
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}
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goto move_on;
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}
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/* We need to split a new table */
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split_pte_block_desc(ptables, pte, desc, level);
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level++;
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} else if (pte_desc_type(pte) == PTE_TABLE_DESC)
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if ((size < level_size) || (virt & (level_size - 1))) {
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/* Range doesn't fit, create subtable */
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table = new_prealloc_table(ptables);
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if (!table) {
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return -ENOMEM;
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}
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/*
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* If entry at current level was already populated
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* then we need to reflect that in the new table.
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*/
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if (is_block_desc(*pte)) {
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populate_table(table, *pte, level + 1);
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}
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/* And link it. */
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set_pte_table_desc(pte, table, level);
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level++;
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continue;
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}
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/* Create block/page descriptor */
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set_pte_block_desc(pte, desc, level);
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move_on:
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virt += level_size;
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desc += level_size;
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size -= level_size;
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/* Range is mapped, start again for next range */
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table = ptables->xlat_tables;
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level = BASE_XLAT_LEVEL;
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}
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return 0;
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}
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/* zephyr execution regions with appropriate attributes */
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@ -292,24 +279,24 @@ static const struct arm_mmu_region mmu_zephyr_regions[] = {
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/* Mark rest of the zephyr execution regions (data, bss, noinit, etc.)
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* cacheable, read-write
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* Note: read-write region is marked execute-ever internally
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* Note: read-write region is marked execute-never internally
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*/
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MMU_REGION_FLAT_ENTRY("zephyr_data",
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(uintptr_t)__kernel_ram_start,
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(uintptr_t)__kernel_ram_size,
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MT_NORMAL | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
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MT_NORMAL | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE | MT_OVERWRITE),
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/* Mark text segment cacheable,read only and executable */
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MMU_REGION_FLAT_ENTRY("zephyr_code",
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(uintptr_t)_image_text_start,
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(uintptr_t)_image_text_size,
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MT_NORMAL | MT_P_RX_U_NA | MT_DEFAULT_SECURE_STATE),
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MT_NORMAL | MT_P_RX_U_NA | MT_DEFAULT_SECURE_STATE | MT_OVERWRITE),
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/* Mark rodata segment cacheable, read only and execute-never */
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MMU_REGION_FLAT_ENTRY("zephyr_rodata",
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(uintptr_t)_image_rodata_start,
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(uintptr_t)_image_rodata_size,
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MT_NORMAL | MT_P_RO_U_NA | MT_DEFAULT_SECURE_STATE),
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MT_NORMAL | MT_P_RO_U_NA | MT_DEFAULT_SECURE_STATE | MT_OVERWRITE),
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};
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static inline void add_arm_mmu_region(struct arm_mmu_ptables *ptables,
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@ -356,6 +343,35 @@ static void setup_page_tables(struct arm_mmu_ptables *ptables)
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}
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}
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/* Translation table control register settings */
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static uint64_t get_tcr(int el)
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{
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uint64_t tcr;
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uint64_t va_bits = CONFIG_ARM64_VA_BITS;
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uint64_t tcr_ps_bits;
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tcr_ps_bits = TCR_PS_BITS;
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if (el == 1) {
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tcr = (tcr_ps_bits << TCR_EL1_IPS_SHIFT);
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/*
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* TCR_EL1.EPD1: Disable translation table walk for addresses
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* that are translated using TTBR1_EL1.
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*/
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tcr |= TCR_EPD1_DISABLE;
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} else
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tcr = (tcr_ps_bits << TCR_EL3_PS_SHIFT);
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tcr |= TCR_T0SZ(va_bits);
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/*
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* Translation table walk is cacheable, inner/outer WBWA and
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* inner shareable
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*/
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tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
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return tcr;
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}
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static void enable_mmu_el1(struct arm_mmu_ptables *ptables, unsigned int flags)
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{
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ARG_UNUSED(flags);
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@ -433,10 +449,10 @@ SYS_INIT(arm_mmu_init, PRE_KERNEL_1,
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#endif
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);
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int arch_mem_map(void *virt, uintptr_t phys, size_t size, uint32_t flags)
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static int __arch_mem_map(void *virt, uintptr_t phys, size_t size, uint32_t flags)
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{
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struct arm_mmu_ptables *ptables;
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uint32_t entry_flags = MT_SECURE | MT_P_RX_U_NA;
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uint32_t entry_flags = MT_SECURE | MT_P_RX_U_NA | MT_OVERWRITE;
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/* Always map in the kernel page tables */
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ptables = &kernel_ptables;
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@ -476,7 +492,15 @@ int arch_mem_map(void *virt, uintptr_t phys, size_t size, uint32_t flags)
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return -ENOTSUP;
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}
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add_map(ptables, "generic", phys, (uintptr_t)virt, size, entry_flags);
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return 0;
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return add_map(ptables, "generic", phys, (uintptr_t)virt, size, entry_flags);
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}
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void arch_mem_map(void *virt, uintptr_t phys, size_t size, uint32_t flags)
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{
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int ret = __arch_mem_map(virt, phys, size, flags);
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if (ret) {
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LOG_ERR("__arch_mem_map() returned %d", ret);
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k_panic();
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}
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}
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@ -21,9 +21,9 @@
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#if DUMP_PTE
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#define L0_SPACE ""
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#define L1_SPACE " "
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#define L2_SPACE " "
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#define L3_SPACE " "
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#define L1_SPACE ". "
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#define L2_SPACE ". . "
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#define L3_SPACE ". . . "
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#define XLAT_TABLE_LEVEL_SPACE(level) \
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(((level) == 0) ? L0_SPACE : \
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((level) == 1) ? L1_SPACE : \
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@ -46,15 +46,14 @@
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/* 48-bit VA address */
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#define VA_SIZE_SHIFT_MAX 48U
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||||
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/* Maximum 4 XLAT table (L0 - L3) */
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#define XLAT_LEVEL_MAX 4U
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/* Maximum 4 XLAT table levels (L0 - L3) */
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#define XLAT_LAST_LEVEL 3U
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||||
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/* The VA shift of L3 depends on the granule size */
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#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT
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/* Number of VA bits to assign to each table (9 bits) */
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#define Ln_XLAT_VA_SIZE_SHIFT ((VA_SIZE_SHIFT_MAX - L3_XLAT_VA_SIZE_SHIFT) / \
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XLAT_LEVEL_MAX)
|
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#define Ln_XLAT_VA_SIZE_SHIFT (PAGE_SIZE_SHIFT - 3)
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/* Starting bit in the VA address for each level */
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#define L2_XLAT_VA_SIZE_SHIFT (L3_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT)
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|
|
@ -63,10 +62,10 @@
|
|||
|
||||
#define LEVEL_TO_VA_SIZE_SHIFT(level) \
|
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(PAGE_SIZE_SHIFT + (Ln_XLAT_VA_SIZE_SHIFT * \
|
||||
((XLAT_LEVEL_MAX - 1) - (level))))
|
||||
(XLAT_LAST_LEVEL - (level))))
|
||||
|
||||
/* Number of entries for each table (512) */
|
||||
#define Ln_XLAT_NUM_ENTRIES (1U << Ln_XLAT_VA_SIZE_SHIFT)
|
||||
#define Ln_XLAT_NUM_ENTRIES ((1U << PAGE_SIZE_SHIFT) / 8U)
|
||||
|
||||
/* Virtual Address Index within a given translation table level */
|
||||
#define XLAT_TABLE_VA_IDX(va_addr, level) \
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@
|
|||
* attrs[5] : Execute Permissions privileged mode (PXN)
|
||||
* attrs[6] : Execute Permissions unprivileged mode (UXN)
|
||||
* attrs[7] : Mirror RO/RW permissions to EL0
|
||||
* attrs[8] : Overwrite existing mapping if any
|
||||
*
|
||||
*/
|
||||
#define MT_PERM_SHIFT 3U
|
||||
|
|
@ -45,6 +46,7 @@
|
|||
#define MT_P_EXECUTE_SHIFT 5U
|
||||
#define MT_U_EXECUTE_SHIFT 6U
|
||||
#define MT_RW_AP_SHIFT 7U
|
||||
#define MT_OVERWRITE_SHIFT 8U
|
||||
|
||||
#define MT_RO (0U << MT_PERM_SHIFT)
|
||||
#define MT_RW (1U << MT_PERM_SHIFT)
|
||||
|
|
@ -61,6 +63,8 @@
|
|||
#define MT_U_EXECUTE (0U << MT_U_EXECUTE_SHIFT)
|
||||
#define MT_U_EXECUTE_NEVER (1U << MT_U_EXECUTE_SHIFT)
|
||||
|
||||
#define MT_OVERWRITE (1U << MT_OVERWRITE_SHIFT)
|
||||
|
||||
#define MT_P_RW_U_RW (MT_RW | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)
|
||||
#define MT_P_RW_U_NA (MT_RW | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)
|
||||
#define MT_P_RO_U_RO (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue