drivers: gpio: npm2100: Add driver for npm2100 pmic
Add gpio driver for npm2100 pmic. Signed-off-by: Audun Korneliussen <audun.korneliussen@nordicsemi.no>
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7 changed files with 290 additions and 2 deletions
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@ -59,6 +59,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX_ALERT gpio_nct38xx_alert.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_NEORV32 gpio_neorv32.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_NPCX gpio_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_NPM1300 gpio_npm1300.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_NPM2100 gpio_npm2100.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_NPM6001 gpio_npm6001.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_NRFX gpio_nrfx.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_NUMAKER gpio_numaker.c)
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@ -146,6 +146,7 @@ source "drivers/gpio/Kconfig.nct38xx"
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source "drivers/gpio/Kconfig.neorv32"
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source "drivers/gpio/Kconfig.npcx"
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source "drivers/gpio/Kconfig.npm1300"
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source "drivers/gpio/Kconfig.npm2100"
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source "drivers/gpio/Kconfig.npm6001"
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source "drivers/gpio/Kconfig.nrfx"
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source "drivers/gpio/Kconfig.numaker"
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19
drivers/gpio/Kconfig.npm2100
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19
drivers/gpio/Kconfig.npm2100
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@ -0,0 +1,19 @@
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_NPM2100
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bool "nPM2100 GPIO driver"
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default y
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depends on DT_HAS_NORDIC_NPM2100_GPIO_ENABLED
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select I2C
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select MFD
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help
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Enable the nPM2100 GPIO driver.
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config GPIO_NPM2100_INIT_PRIORITY
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int "nPM2100 GPIO driver initialization priority"
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depends on GPIO_NPM2100
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default 80
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help
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Initialization priority for the nPM2100 GPIO driver. It must be
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greater than the I2C controller init priority.
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182
drivers/gpio/gpio_npm2100.c
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182
drivers/gpio/gpio_npm2100.c
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@ -0,0 +1,182 @@
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nordic_npm2100_gpio
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#include <errno.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/dt-bindings/gpio/nordic-npm2100-gpio.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/util_macro.h>
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#define NPM2100_GPIO_CONFIG 0x80U
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#define NPM2100_GPIO_USAGE 0x83U
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#define NPM2100_GPIO_OUTPUT 0x86U
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#define NPM2100_GPIO_READ 0x89U
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#define NPM2100_GPIO_PINS 2U
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#define NPM2100_GPIO_CONFIG_INPUT 0x01U
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#define NPM2100_GPIO_CONFIG_OUTPUT 0x02U
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#define NPM2100_GPIO_CONFIG_OPENDRAIN 0x04U
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#define NPM2100_GPIO_CONFIG_PULLDOWN 0x08U
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#define NPM2100_GPIO_CONFIG_PULLUP 0x10U
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#define NPM2100_GPIO_CONFIG_DRIVE 0x20U
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#define NPM2100_GPIO_CONFIG_DEBOUNCE 0x40U
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struct gpio_npm2100_config {
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struct gpio_driver_config common;
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struct i2c_dt_spec i2c;
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};
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struct gpio_npm2100_data {
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struct gpio_driver_data common;
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};
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static int gpio_npm2100_port_get_raw(const struct device *dev, uint32_t *value)
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{
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const struct gpio_npm2100_config *config = dev->config;
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uint8_t data;
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int ret;
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ret = i2c_reg_read_byte_dt(&config->i2c, NPM2100_GPIO_READ, &data);
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if (ret < 0) {
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return ret;
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}
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*value = data;
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return 0;
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}
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static int gpio_npm2100_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_npm2100_config *config = dev->config;
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int ret = 0;
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for (size_t idx = 0; idx < NPM2100_GPIO_PINS; idx++) {
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if ((mask & BIT(idx)) != 0U) {
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i2c_reg_write_byte_dt(&config->i2c, NPM2100_GPIO_OUTPUT + idx,
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!!(value & BIT(idx)));
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if (ret != 0U) {
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return ret;
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}
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}
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}
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return ret;
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}
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static int gpio_npm2100_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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return gpio_npm2100_port_set_masked_raw(dev, pins, pins);
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}
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static int gpio_npm2100_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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return gpio_npm2100_port_set_masked_raw(dev, pins, 0U);
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}
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static inline int gpio_npm2100_configure(const struct device *dev, gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_npm2100_config *config = dev->config;
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uint8_t reg = 0U;
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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if (pin >= NPM2100_GPIO_PINS) {
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return -EINVAL;
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}
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/* Set initial state if defined */
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if ((flags & (GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH)) != 0U) {
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int ret = i2c_reg_write_byte_dt(&config->i2c, NPM2100_GPIO_OUTPUT + pin,
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!!(flags & GPIO_OUTPUT_INIT_HIGH));
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if (ret < 0) {
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return ret;
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}
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}
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/* Set pin configuration */
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if ((flags & GPIO_INPUT) != 0U) {
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reg |= NPM2100_GPIO_CONFIG_INPUT;
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}
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if ((flags & GPIO_OUTPUT) != 0U) {
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reg |= NPM2100_GPIO_CONFIG_OUTPUT;
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}
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if ((flags & GPIO_SINGLE_ENDED) != 0U) {
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reg |= NPM2100_GPIO_CONFIG_OPENDRAIN;
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}
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if ((flags & GPIO_PULL_UP) != 0U) {
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reg |= NPM2100_GPIO_CONFIG_PULLUP;
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}
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if ((flags & GPIO_PULL_DOWN) != 0U) {
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reg |= NPM2100_GPIO_CONFIG_PULLDOWN;
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}
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if ((flags & NPM2100_GPIO_DRIVE_HIGH) != 0U) {
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reg |= NPM2100_GPIO_CONFIG_DRIVE;
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}
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if ((flags & NPM2100_GPIO_DEBOUNCE_ON) != 0U) {
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reg |= NPM2100_GPIO_CONFIG_DEBOUNCE;
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}
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return i2c_reg_write_byte_dt(&config->i2c, NPM2100_GPIO_CONFIG + pin, reg);
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}
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static int gpio_npm2100_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
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{
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int ret;
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uint32_t value;
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ret = gpio_npm2100_port_get_raw(dev, &value);
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if (ret < 0) {
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return ret;
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}
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return gpio_npm2100_port_set_masked_raw(dev, pins, ~value);
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}
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static DEVICE_API(gpio, gpio_npm2100_api) = {
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.pin_configure = gpio_npm2100_configure,
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.port_get_raw = gpio_npm2100_port_get_raw,
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.port_set_masked_raw = gpio_npm2100_port_set_masked_raw,
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.port_set_bits_raw = gpio_npm2100_port_set_bits_raw,
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.port_clear_bits_raw = gpio_npm2100_port_clear_bits_raw,
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.port_toggle_bits = gpio_npm2100_port_toggle_bits,
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};
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static int gpio_npm2100_init(const struct device *dev)
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{
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const struct gpio_npm2100_config *config = dev->config;
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if (!i2c_is_ready_dt(&config->i2c)) {
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return -ENODEV;
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}
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return 0;
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}
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#define GPIO_NPM2100_DEFINE(n) \
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static const struct gpio_npm2100_config gpio_npm2100_config##n = { \
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.common = \
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{ \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.i2c = I2C_DT_SPEC_GET(DT_INST_PARENT(n))}; \
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\
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static struct gpio_npm2100_data gpio_npm2100_data##n; \
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\
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DEVICE_DT_INST_DEFINE(n, &gpio_npm2100_init, NULL, &gpio_npm2100_data##n, \
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&gpio_npm2100_config##n, POST_KERNEL, \
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CONFIG_GPIO_NPM2100_INIT_PRIORITY, &gpio_npm2100_api);
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DT_INST_FOREACH_STATUS_OKAY(GPIO_NPM2100_DEFINE)
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12
dts/bindings/gpio/nordic,npm2100-gpio.yaml
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12
dts/bindings/gpio/nordic,npm2100-gpio.yaml
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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description: nPM2100 GPIO Controller
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compatible: "nordic,npm2100-gpio"
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include: gpio-controller.yaml
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gpio-cells:
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- pin
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- flags
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61
include/zephyr/dt-bindings/gpio/nordic-npm2100-gpio.h
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61
include/zephyr/dt-bindings/gpio/nordic-npm2100-gpio.h
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@ -0,0 +1,61 @@
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/*
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* Copyright (c) 2023 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM2100_GPIO_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM2100_GPIO_H_
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/**
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* @brief nPM2100-specific GPIO Flags
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* @defgroup gpio_interface_npm2100 nPM2100-specific GPIO Flags
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*
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* The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
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* follows:
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*
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* - Bit 8: Drive strength (0=1mA, 1=6mA)
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* - Bit 9: Debounce (0=OFF, 1=ON)
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*
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* @ingroup gpio_interface
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* @{
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*/
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/**
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* @name nPM2100 GPIO drive strength flags
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* @brief nPM2100 GPIO drive strength flags
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* @{
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*/
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/** @cond INTERNAL_HIDDEN */
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/** Drive mode field mask */
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#define NPM2100_GPIO_DRIVE_MSK 0x0100U
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/** @endcond */
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/** Normal drive */
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#define NPM2100_GPIO_DRIVE_NORMAL (0U << 8U)
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/** High drive */
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#define NPM2100_GPIO_DRIVE_HIGH (1U << 8U)
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/** @} */
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/**
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* @name nPM2100 GPIO debounce flags
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* @brief nPM2100 GPIO debounce flags
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* @{
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*/
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/** @cond INTERNAL_HIDDEN */
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/** Debounce field mask */
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#define NPM2100_GPIO_DEBOUNCE_MSK 0x0200U
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/** @endcond */
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/** Normal drive */
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#define NPM2100_GPIO_DEBOUNCE_OFF (0U << 9U)
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/** High drive */
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#define NPM2100_GPIO_DEBOUNCE_ON (1U << 9U)
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/** @} */
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/** @} */
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM2100_GPIO_H_ */
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@ -338,9 +338,9 @@
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};
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};
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it8801_mfd: it8801@38 {
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it8801_mfd: it8801@14 {
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compatible = "ite,it8801-mfd";
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reg = <0x38>;
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reg = <0x14>;
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irq-gpios = <&test_gpio 1 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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test_i2c_npm2100: pmic@15 {
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compatible = "nordic,npm2100";
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reg = <0x15>;
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npm2100_gpio: gpio-controller {
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compatible = "nordic,npm2100-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <2>;
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};
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};
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};
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nct3807_alert_1 {
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