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riscv: add a qemu_riscv64 board

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This emulates a RISC-V in 64-bit mode on a SiFive FE310 dev board.
Memory is tight so a few tests had to be disabled due to the extra
memory usage compared to qemu_riscv32.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2019-07-18 23:07:45 -04:00 • committed by Kumar Gala
commit 7f74825958
11 changed files with 191 additions and 1 deletions
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tests/lib/rbtree/testcase.yaml
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@ -2,3 +2,4 @@ tests:
libraries.data_structures.rbtree:
tags: rbtree
filter: not CONFIG_MISRA_SANE
platform_exclude: qemu_riscv64