dts: clock_control: add mp2 rcc binding

Introduce DeviceTree binding for the STM32MP2 RCC clock controller,
enabling support for STM32MP2-specific clock configuration in Zephyr.
Update Kconfig.stm32 to add a dependency on STM32MP2 configuration,
allowing the use of STM32 LL RCC features when targeting STM32MP2
devices.
Add header for STM32MP2 per peripheral clock definitions.

Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>

boards/st/stm32mp257f_ev1/stm32mp257f_ev1_stm32mp257fxx_m33_defconfig

@@ -4,7 +4,5 @@
 # Enable MPU
 CONFIG_ARM_MPU=y
 
-CONFIG_CLOCK_CONTROL=n
-
 # Enable HW stack protection
 CONFIG_HW_STACK_PROTECTION=y

drivers/clock_control/Kconfig.stm32

@@ -2,6 +2,7 @@
 
 # Copyright (c) 2017 Linaro
 # Copyright (c) 2017 RnDity Sp. z o.o.
+# Copyright (C) 2025 Savoir-faire Linux, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
 menuconfig CLOCK_CONTROL_STM32_CUBE
@@ -9,8 +10,9 @@ menuconfig CLOCK_CONTROL_STM32_CUBE
 	depends on SOC_FAMILY_STM32
 	default y
 	select USE_STM32_LL_UTILS
-	select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32MP13X || SOC_SERIES_STM32H7X || \
+	select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32MP13X || \
-		SOC_SERIES_STM32H7RSX || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || \
+		SOC_SERIES_STM32MP2X || SOC_SERIES_STM32H7X || SOC_SERIES_STM32H7RSX || \
+		SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || \
 		SOC_SERIES_STM32N6X)
 	select RUNTIME_NMI if ($(dt_nodelabel_enabled,clk_hse) && \
 		$(dt_nodelabel_bool_prop,clk_hse,css-enabled))

dts/bindings/clock/st,stm32mp2-rcc.yaml

@@ -0,0 +1,33 @@
+# Copyright (C) 2025 Savoir-faire Linux, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32MP2 RCC (Reset and Clock controller).
+
+  On STM32MP2 platforms, the clock tree is configured by the Cortex-A35 core.
+  As a consequence, the only property to be set in devicetree node is the
+  clock-frequency.
+
+  As for the peripherals, the clocks are configured per peripheral in the
+  corresponding device tree node. The clock controller is responsible for
+  enabling/disabling the clocks for the peripherals, when allowed by the
+  Resource Isolation Framework(RIF) peripheral, configured by the cortex-A35
+  core.
+
+  To declare a peripheral "PERx" clock in the dtsi, you can follow the example
+  below:
+    PERx {
+      ...
+      clocks = <&rcc STM32_CLOCK(PERx, STM32_CLK)>;
+      ...
+    };
+
+compatible: "st,stm32mp2-rcc"
+
+include:
+  - name: st,stm32-rcc.yaml
+    property-blocklist:
+      - ahb-prescaler
+      - apb1-prescaler
+      - apb2-prescaler
+      - undershoot-prevention

include/zephyr/dt-bindings/clock/stm32mp2_clock.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2025 Savoir-faire Linux, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP2_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP2_CLOCK_H_
+
+#include "stm32_common_clocks.h"
+
+/* Undefine the common clocks macro */
+#undef STM32_CLOCK
+
+/**
+ * Pack RCC clock register offset and bit in two 32-bit values
+ * as expected for the Device Tree `clocks` property on STM32.
+ *
+ * @param per STM32 Peripheral name (expands to STM32_CLOCK_PERIPH_{PER})
+ * @param bit Clock bit
+ */
+#define STM32_CLOCK(per, bit) (STM32_CLOCK_PERIPH_##per) (1 << bit)
+
+/* Clock reg */
+#define STM32_CLK		1U
+#define STM32_LP_CLK		2U
+
+/* GPIO Peripheral */
+#define STM32_CLOCK_PERIPH_GPIOA	0x52C
+#define STM32_CLOCK_PERIPH_GPIOB	0x530
+#define STM32_CLOCK_PERIPH_GPIOC	0x534
+#define STM32_CLOCK_PERIPH_GPIOD	0x538
+#define STM32_CLOCK_PERIPH_GPIOE	0x53C
+#define STM32_CLOCK_PERIPH_GPIOF	0x540
+#define STM32_CLOCK_PERIPH_GPIOG	0x544
+#define STM32_CLOCK_PERIPH_GPIOH	0x548
+#define STM32_CLOCK_PERIPH_GPIOI	0x54C
+#define STM32_CLOCK_PERIPH_GPIOJ	0x550
+#define STM32_CLOCK_PERIPH_GPIOK	0x554
+#define STM32_CLOCK_PERIPH_GPIOZ	0x558
+
+#define STM32_CLOCK_PERIPH_MIN	STM32_CLOCK_PERIPH_GPIOA
+#define STM32_CLOCK_PERIPH_MAX	STM32_CLOCK_PERIPH_GPIOZ
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP2_CLOCK_H_ */