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modules: hal_nxp: Move hal_nxp glue layer to zephyr repo

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Move hal_nxp glue layer to zephyr repo.
Fix build warnings and failures caused by hal_nxp upgrade.
Update manifest to contain hal_nxp changes.

Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
This commit is contained in:
Zhaoxiang Jin 2025-03-12 12:12:31 +08:00 • committed by Benjamin Cabé
commit 7ed7cd191a
48 changed files with 1394 additions and 69 deletions
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3
soc/nxp/imx/imx8m/Kconfig
View file

@ -93,6 +93,9 @@ config SOC_MIMX8MQ6_M4
config MCUX_CORE_SUFFIX
default "_ca53" if SOC_MIMX8MM6_A53 || SOC_MIMX8MN6_A53 || SOC_MIMX8ML8_A53
default "_dsp" if SOC_MIMX8ML8_ADSP
default "_cm4" if SOC_MIMX8MM6_M4
default "_cm7" if SOC_MIMX8ML8_M7
default "_cm4" if SOC_MIMX8MQ6_M4
if SOC_MIMX8ML8_M7

11
soc/nxp/imxrt/imxrt118x/CMakeLists.txt
View file

@ -1,5 +1,5 @@
#
# Copyright 2024 NXP
# Copyright 2024-2025 NXP
#
# SPDX-License-Identifier: Apache-2.0
#
@ -24,4 +24,13 @@ if(CONFIG_MEMC_MCUX_FLEXSPI)
endif()
endif()
if((CONFIG_NXP_IMXRT_BOOT_HEADER) AND (CONFIG_BOOT_FLEXSPI_NOR))
set(RT118x_DEVICE_BOOT_HEADER_DIR
"${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189")
zephyr_library_sources(${RT118x_DEVICE_BOOT_HEADER_DIR}/xip/fsl_flexspi_nor_boot.c)
zephyr_library_include_directories(${RT118x_DEVICE_BOOT_HEADER_DIR}/xip)
zephyr_library_include_directories(${RT118x_DEVICE_BOOT_HEADER_DIR})
endif()
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

4
soc/nxp/imxrt/imxrt118x/soc.c
View file

@ -340,7 +340,7 @@ __weak void clock_init(void)
#endif /* CONFIG_COUNTER_MCUX_GPT */
#ifdef CONFIG_MCUX_ACMP
#if defined(CONFIG_COMPARATOR_MCUX_ACMP) || defined(CONFIG_SENSOR_MCUX_ACMP)
#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp1)) \
|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp2)) \
@ -352,7 +352,7 @@ __weak void clock_init(void)
CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
#endif
#endif /* CONFIG_MCUX_ACMP */
#endif /* CONFIG_COMPARATOR_MCUX_ACMP || CONFIG_SENSOR_MCUX_ACMP */
#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0)
/* Configure ENET using SYS_PLL1_DIV2_CLK */

3
soc/nxp/imxrt/imxrt11xx/power.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, NXP
* Copyright (c) 2021, 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -57,7 +57,6 @@ static void gpc_set_transition_flow(void)
gpc_tran_step_config_t step_cfg;
step_cfg.enableStep = true;
step_cfg.cntMode = kGPC_StepCounterDisableMode;
/* Cortex M7 */
GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,

8
soc/nxp/imxrt/imxrt11xx/soc.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2021-2024 NXP
* Copyright 2021-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -19,7 +19,7 @@
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_CPU_CORTEX_M7)
#include <fsl_flexspi_nor_boot.h>
#endif
#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
@ -127,7 +127,7 @@ usb_phy_config_struct_t usbPhyConfig = {
};
#endif
#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER
#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_CPU_CORTEX_M7)
const __imx_boot_data_section BOOT_DATA_T boot_data = {
#ifdef CONFIG_XIP
.start = CONFIG_FLASH_BASE_ADDRESS,
@ -494,7 +494,7 @@ __weak void clock_init(void)
#endif
#endif
#ifdef CONFIG_MCUX_ACMP
#if defined(CONFIG_COMPARATOR_MCUX_ACMP) || defined(CONFIG_SENSOR_MCUX_ACMP)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp1))
/* Configure ACMP1 using Osc48MDiv2*/
rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;

11
soc/nxp/imxrt/imxrt7xx/cm33/flash_clock_setup.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2024 NXP
* Copyright 2024-2025 NXP
* SPDX-License-Identifier: Apache-2.0
*/
@ -88,12 +88,9 @@ static void flash_init(XSPI_Type *base, CACHE64_CTRL_Type *cache)
/* Enable subordinate as auto update mode. */
base->DLLCR[0] |= XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK;
/* program DLL to desired delay. */
base->DLLCR[0] |=
XSPI_DLLCR_DLLRES(FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_DISABLE_RES) |
XSPI_DLLCR_DLL_REFCNTR(
FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_DISABLED_REF_COUNTER) |
XSPI_DLLCR_SLV_FINE_OFFSET(0) | XSPI_DLLCR_SLV_DLY_OFFSET(0) |
XSPI_DLLCR_FREQEN(1U);
base->DLLCR[0] |= XSPI_DLLCR_DLLRES(FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_RES) |
XSPI_DLLCR_DLL_REFCNTR(2U) | XSPI_DLLCR_DLL_CDL8(1U) | XSPI_DLLCR_FREQEN(1U) |
XSPI_DLLCR_SLV_FINE_OFFSET(0) | XSPI_DLLCR_SLV_DLY_OFFSET(0);
/* Load above settings into delay chain. */
base->DLLCR[0] |= XSPI_DLLCR_SLV_UPD_MASK;
base->DLLCR[0] |= XSPI_DLLCR_DLLEN_MASK;