diff --git a/arch/arm/soc/st_stm32/stm32f3/soc.c b/arch/arm/soc/st_stm32/stm32f3/soc.c
index 27ebea9a4d9..9a4358ab5a4 100644
--- a/arch/arm/soc/st_stm32/stm32f3/soc.c
+++ b/arch/arm/soc/st_stm32/stm32f3/soc.c
@@ -42,8 +42,12 @@ static int stm32f3_init(struct device *arg)
 	irq_unlock(key);
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+	/* At reset, System core clock is set to 4MHz */
+	SystemCoreClock = 4000000;
+#else
 	SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
-
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
 	return 0;
 }
 
diff --git a/arch/arm/soc/st_stm32/stm32f3/soc.h b/arch/arm/soc/st_stm32/stm32f3/soc.h
index e6474735fbc..85bdd58cd9b 100644
--- a/arch/arm/soc/st_stm32/stm32f3/soc.h
+++ b/arch/arm/soc/st_stm32/stm32f3/soc.h
@@ -52,6 +52,13 @@ enum stm32f3x_pin_config_mode {
 #include <stm32f3xx_ll_usart.h>
 #endif
 
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+#include <stm32f3xx_ll_utils.h>
+#include <stm32f3xx_ll_bus.h>
+#include <stm32f3xx_ll_rcc.h>
+#include <stm32f3xx_ll_system.h>
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32F3_SOC_H_ */
diff --git a/arch/arm/soc/st_stm32/stm32f3/soc_gpio.c b/arch/arm/soc/st_stm32/stm32f3/soc_gpio.c
index a30205c9c6d..90758118a57 100644
--- a/arch/arm/soc/st_stm32/stm32f3/soc_gpio.c
+++ b/arch/arm/soc/st_stm32/stm32f3/soc_gpio.c
@@ -188,7 +188,16 @@ int stm32_gpio_enable_int(int port, int pin)
 	struct device *clk =
 		device_get_binding(STM32_CLOCK_CONTROL_NAME);
 
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+	struct stm32_pclken pclken = {
+		.bus = STM32_CLOCK_BUS_APB2,
+		.enr = LL_APB2_GRP1_PERIPH_SYSCFG
+	};
+
+	clock_control_on(clk, (clock_control_subsys_t *) &pclken);
+#else
 	clock_control_on(clk, UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_SYSCFG));
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
 
 	int shift = 0;