diff --git a/dts/arm/st/g0/stm32g0.dtsi b/dts/arm/st/g0/stm32g0.dtsi new file mode 100644 index 00000000000..3236f3a7225 --- /dev/null +++ b/dts/arm/st/g0/stm32g0.dtsi @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2019 Philippe Retornaz + * Copyright (c) 2019 ST Microelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m0+"; + reg = <0>; + }; + }; + + sram0: memory@20000000 { + device_type = "memory"; + compatible = "mmio-sram"; + }; + + soc { + flash-controller@40022000 { + compatible = "st,stm32g0-flash-controller"; + label = "FLASH_CTRL"; + reg = <0x40022000 0x400>; + interrupts = <3 0>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + label = "FLASH_STM32"; + + write-block-size = <8>; + erase-block-size = <2048>; + }; + }; + + }; +}; + +&nvic { + arm,num-irq-priority-bits = <2>; +}; \ No newline at end of file diff --git a/dts/arm/st/g0/stm32g071.dtsi b/dts/arm/st/g0/stm32g071.dtsi new file mode 100644 index 00000000000..49c68eeaaae --- /dev/null +++ b/dts/arm/st/g0/stm32g071.dtsi @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2019 Philippe Retornaz + * Copyright (c) 2019 ST Microelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/dts/arm/st/g0/stm32g071Xb.dtsi b/dts/arm/st/g0/stm32g071Xb.dtsi new file mode 100644 index 00000000000..3e437d6bc3c --- /dev/null +++ b/dts/arm/st/g0/stm32g071Xb.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2019 Philippe Retornaz + * Copyright (c) 2019 ST Microelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(36)>; + }; + + soc { + flash-controller@40022000 { + flash0: flash@8000000 { + reg = <0x08000000 DT_SIZE_K(128)>; + }; + }; + }; +}; \ No newline at end of file diff --git a/soc/arm/st_stm32/stm32g0/CMakeLists.txt b/soc/arm/st_stm32/stm32g0/CMakeLists.txt new file mode 100644 index 00000000000..ac3ba70ace6 --- /dev/null +++ b/soc/arm/st_stm32/stm32g0/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series new file mode 100644 index 00000000000..a9489e220cf --- /dev/null +++ b/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series @@ -0,0 +1,20 @@ +# Kconfig - STMicroelectronics STM32G0 MCU line +# +# Copyright (c) 2019 Philippe Retornaz +# Copyright (c) 2019 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_STM32G0X + +source "soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0*" + +config SOC_SERIES + default "stm32g0" + +if GPIO_STM32 + +endif # GPIO_STM32 + +endif # SOC_SERIES_STM32G0X diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g071rb b/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g071rb new file mode 100644 index 00000000000..841a71ed0c5 --- /dev/null +++ b/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g071rb @@ -0,0 +1,22 @@ +# Kconfig - STMicroelectronics STM32G071RB MCU +# +# Copyright (c) 2019 Philippe Retornaz +# Copyright (c) 2019 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_STM32G071XX + +config SOC + string + default "stm32g071xx" + +config NUM_IRQS + int + default 32 + +if GPIO_STM32 + +endif # GPIO_STM32 +endif # SOC_STM32G071XX diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.series b/soc/arm/st_stm32/stm32g0/Kconfig.series new file mode 100644 index 00000000000..7a9f234869d --- /dev/null +++ b/soc/arm/st_stm32/stm32g0/Kconfig.series @@ -0,0 +1,18 @@ +# Kconfig - STMicroelectronics STM32G0 MCU series +# +# Copyright (c) 2019 Philippe Retornaz +# Copyright (c) 2019 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_STM32G0X + bool "STM32G0x Series MCU" + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_VTOR + select SOC_FAMILY_STM32 + select HAS_STM32CUBE + select CPU_CORTEX_M_HAS_SYSTICK + select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL + help + Enable support for STM32G0 MCU series diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.soc b/soc/arm/st_stm32/stm32g0/Kconfig.soc new file mode 100644 index 00000000000..2f1c8a02247 --- /dev/null +++ b/soc/arm/st_stm32/stm32g0/Kconfig.soc @@ -0,0 +1,17 @@ +# Kconfig - STMicroelectronics STM32G0 MCU line +# +# Copyright (c) 2019 Philippe Retornaz +# Copyright (c) 2019 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +choice +prompt "STM32G0x MCU Selection" +depends on SOC_SERIES_STM32G0X + +config SOC_STM32G071XX + bool "STM32G071XX" + + +endchoice diff --git a/soc/arm/st_stm32/stm32g0/dts_fixup.h b/soc/arm/st_stm32/stm32g0/dts_fixup.h new file mode 100644 index 00000000000..4954ef70a4d --- /dev/null +++ b/soc/arm/st_stm32/stm32g0/dts_fixup.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2019 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* SoC level DTS fixup file */ + +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS + +/* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32g0/linker.ld b/soc/arm/st_stm32/stm32g0/linker.ld new file mode 100644 index 00000000000..2a9e31923f7 --- /dev/null +++ b/soc/arm/st_stm32/stm32g0/linker.ld @@ -0,0 +1,10 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2019 Philippe Retornaz + * Copyright (c) 2019 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/st_stm32/stm32g0/soc.c b/soc/arm/st_stm32/stm32g0/soc.c new file mode 100644 index 00000000000..a85413fb729 --- /dev/null +++ b/soc/arm/st_stm32/stm32g0/soc.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2019 Philippe Retornaz + * Copyright (c) 2019 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for STM32G0 processor + */ + +#include +#include +#include +#include +#include +#include + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int stm32g0_init(struct device *arg) +{ + u32_t key; + + ARG_UNUSED(arg); + + key = irq_lock(); + + /* Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + irq_unlock(key); + + /* Update CMSIS SystemCoreClock variable (HCLK) */ + /* At reset, system core clock is set to 16 MHz from HSI */ + SystemCoreClock = 16000000; + + return 0; +} + +SYS_INIT(stm32g0_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/st_stm32/stm32g0/soc.h b/soc/arm/st_stm32/stm32g0/soc.h new file mode 100644 index 00000000000..021abd1de98 --- /dev/null +++ b/soc/arm/st_stm32/stm32g0/soc.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2019 Philippe Retornaz + * Copyright (c) 2019 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the STM32G0 family processors. + * + * Based on reference manual: + * STM32G0X advanced ARM ® -based 32-bit MCUs + * + * Chapter 2.2: Memory organization + */ + + +#ifndef _STM32G0_SOC_H_ +#define _STM32G0_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +/* ARM CMSIS definitions must be included before kernel_includes.h. + * Therefore, it is essential to include kernel_includes.h after including + * core SOC-specific headers. + */ +#include + +#include + +#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE +#include +#include +#include +#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ + +#endif /* !_ASMLANGUAGE */ + +#endif /* _STM32G0_SOC_H_ */