doc: release: v2.5.0 release notes for ARM AARCH32
Zephyr v2.5.0 release notes for AARCH32 architecture. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
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@ -164,10 +164,22 @@ Architectures
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* AARCH32
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* Introduced the functionality for chain-loadable Zephyr
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fimrmware images to force the initialization of internal
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firmware images to force the initialization of internal
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architecture state during early system boot (Cortex-M).
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* Changed the default Floating Point Services mode to
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Shared FP registers mode.
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* Enhanced Cortex-M Shared FP register mode by implementing
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dynamic lazy FP register stacking in threads.
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* Added preliminary support for Cortex-R7 variant.
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* Fixed inline assembly code in Cortex-M system calls.
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* Enhanced and fixed Cortex-M TCS support.
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* Enabled interrupts before switching to main in single-thread
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Cortex-M builds (CONFIG_MULTITHREADING=n).
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* Fixed vector table relocation in non-XIP Cortex-M builds.
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* Fixed exception exit routine for fatal error exceptions in
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Cortex-R.
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* Fixed interrupt nesting in ARMv7-R architecture.
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* AARCH64
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