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soc: add npck soc driver

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For npck3m8k:
1. Update code ram from 320KB to 416KB (0x1005_8000~0x100B_FFFF).
2. Update data ram from 32KB to 64KB.
3. Move fiudiv from hfcbcd1 to hfcbcd2 register

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
Alvis Sun 2025-04-21 18:24:55 +08:00 • committed by Benjamin Cabé
commit 7e23f8b408
19 changed files with 2532 additions and 39 deletions
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9
soc/nuvoton/npcx/npcx9/soc.h
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@ -25,6 +25,9 @@
#define NPCX_WKST_OFFSET(n) (0x006 + (n * 0x010))
#define NPCX_WKINEN_OFFSET(n) (0x007 + (n * 0x010))
/* NPCX9 PMC multi-registers */
#define NPCX_PWDWN_CTL_OFFSET(n) (((n - 1) < 6) ? (0x008 + (n - 1)) : (0x01e + (n - 1)))
/* NPCX9 ADC multi-registers */
#define NPCX_CHNDAT_OFFSET(n) (0x040 + (n * 2))
#define NPCX_THRCTL_OFFSET(n) (0x060 + (n * 2))
@ -53,4 +56,10 @@
#include <soc_pins.h>
#include <soc_power.h>
/* NPCX9 Clock prescaler configurations */
#define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL)
#define VAL_HFCBCD (FIUDIV_VAL << 4)
#define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4))
#define VAL_HFCBCD2 (APB3DIV_VAL | (APB4DIV_VAL << 4))
#endif /* _NUVOTON_NPCX_SOC_H_ */