soc/qemu_xtensa_dc233c: Use the automatically-generated vector region
Remove all the hard-configured absolute addresses and zillions of tiny ELF segments in favor of the auto-generated vector region, which is guaranteed correct as long as core-isa.h is matched to the target. Signed-off-by: Andy Ross <andyross@google.com>
This commit is contained in:
Andy Ross
David Leach
parent
3aeefd2250
commit
7dd4c4d312
1 changed files with 5 additions and 171 deletions
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@ -45,25 +45,7 @@
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MEMORY
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{
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sram0_0_seg : org = 0x00002000, len = 0x178
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sram0_1_seg : org = 0x00002178, len = 0x8
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sram0_2_seg : org = 0x00002180, len = 0x38
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sram0_3_seg : org = 0x000021B8, len = 0x8
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sram0_4_seg : org = 0x000021C0, len = 0x38
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sram0_5_seg : org = 0x000021F8, len = 0x8
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sram0_6_seg : org = 0x00002200, len = 0x38
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sram0_7_seg : org = 0x00002238, len = 0x8
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sram0_8_seg : org = 0x00002240, len = 0x38
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sram0_9_seg : org = 0x00002278, len = 0x8
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sram0_10_seg : org = 0x00002280, len = 0x38
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sram0_11_seg : org = 0x000022B8, len = 0x8
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sram0_12_seg : org = 0x000022C0, len = 0x38
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sram0_13_seg : org = 0x000022F8, len = 0x8
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sram0_14_seg : org = 0x00002300, len = 0x38
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sram0_15_seg : org = 0x00002338, len = 0x8
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sram0_16_seg : org = 0x00002340, len = 0x38
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sram0_17_seg : org = 0x00002378, len = 0x48
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sram0_18_seg : org = 0x000023C0, len = 0x40
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vectors : org = 0x00002000, len = 0x2400
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#ifdef CONFIG_XTENSA_MMU
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vec_helpers : org = 0x00002400, len = (PHYS_RAM_ADDR - 0x00002400)
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#endif
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@ -87,26 +69,7 @@ MEMORY
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PHDRS
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{
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sram0_0_phdr PT_LOAD;
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sram0_1_phdr PT_LOAD;
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sram0_2_phdr PT_LOAD;
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sram0_3_phdr PT_LOAD;
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sram0_4_phdr PT_LOAD;
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sram0_5_phdr PT_LOAD;
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sram0_6_phdr PT_LOAD;
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sram0_7_phdr PT_LOAD;
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sram0_8_phdr PT_LOAD;
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sram0_9_phdr PT_LOAD;
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sram0_10_phdr PT_LOAD;
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sram0_11_phdr PT_LOAD;
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sram0_12_phdr PT_LOAD;
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sram0_13_phdr PT_LOAD;
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sram0_14_phdr PT_LOAD;
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sram0_15_phdr PT_LOAD;
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sram0_16_phdr PT_LOAD;
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sram0_17_phdr PT_LOAD;
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sram0_18_phdr PT_LOAD;
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vectors_phdr PT_LOAD;
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#ifdef CONFIG_XTENSA_MMU
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vec_helpers_phdr PT_LOAD;
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#endif
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@ -154,138 +117,9 @@ SECTIONS
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#include <zephyr/linker/intlist.ld>
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#endif
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.WindowVectors.text : ALIGN(4)
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{
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_WindowVectors_text_start = ABSOLUTE(.);
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KEEP (*(.WindowVectors.text))
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_WindowVectors_text_end = ABSOLUTE(.);
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} >sram0_0_seg :sram0_0_phdr
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.Level2InterruptVector.literal : ALIGN(4)
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{
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_Level2InterruptVector_literal_start = ABSOLUTE(.);
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*(.Level2InterruptVector.literal)
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_Level2InterruptVector_literal_end = ABSOLUTE(.);
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} >sram0_1_seg :sram0_1_phdr
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.Level2InterruptVector.text : ALIGN(4)
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{
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_Level2InterruptVector_text_start = ABSOLUTE(.);
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KEEP (*(.Level2InterruptVector.text))
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_Level2InterruptVector_text_end = ABSOLUTE(.);
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} >sram0_2_seg :sram0_2_phdr
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.Level3InterruptVector.literal : ALIGN(4)
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{
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_Level3InterruptVector_literal_start = ABSOLUTE(.);
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*(.Level3InterruptVector.literal)
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_Level3InterruptVector_literal_end = ABSOLUTE(.);
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} >sram0_3_seg :sram0_3_phdr
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.Level3InterruptVector.text : ALIGN(4)
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{
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_Level3InterruptVector_text_start = ABSOLUTE(.);
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KEEP (*(.Level3InterruptVector.text))
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_Level3InterruptVector_text_end = ABSOLUTE(.);
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} >sram0_4_seg :sram0_4_phdr
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.Level4InterruptVector.literal : ALIGN(4)
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{
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_Level4InterruptVector_literal_start = ABSOLUTE(.);
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*(.Level4InterruptVector.literal)
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_Level4InterruptVector_literal_end = ABSOLUTE(.);
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} >sram0_5_seg :sram0_5_phdr
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.Level4InterruptVector.text : ALIGN(4)
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{
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_Level4InterruptVector_text_start = ABSOLUTE(.);
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KEEP (*(.Level4InterruptVector.text))
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_Level4InterruptVector_text_end = ABSOLUTE(.);
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} >sram0_6_seg :sram0_6_phdr
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.Level5InterruptVector.literal : ALIGN(4)
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{
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_Level5InterruptVector_literal_start = ABSOLUTE(.);
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*(.Level5InterruptVector.literal)
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_Level5InterruptVector_literal_end = ABSOLUTE(.);
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} >sram0_7_seg :sram0_7_phdr
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.Level5InterruptVector.text : ALIGN(4)
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{
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_Level5InterruptVector_text_start = ABSOLUTE(.);
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KEEP (*(.Level5InterruptVector.text))
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_Level5InterruptVector_text_end = ABSOLUTE(.);
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} >sram0_8_seg :sram0_8_phdr
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.DebugExceptionVector.literal : ALIGN(4)
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{
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_DebugExceptionVector_literal_start = ABSOLUTE(.);
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*(.DebugExceptionVector.literal)
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_DebugExceptionVector_literal_end = ABSOLUTE(.);
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} >sram0_9_seg :sram0_9_phdr
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.DebugExceptionVector.text : ALIGN(4)
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{
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_DebugExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.DebugExceptionVector.text))
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_DebugExceptionVector_text_end = ABSOLUTE(.);
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} >sram0_10_seg :sram0_10_phdr
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.NMIExceptionVector.literal : ALIGN(4)
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{
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_NMIExceptionVector_literal_start = ABSOLUTE(.);
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*(.NMIExceptionVector.literal)
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_NMIExceptionVector_literal_end = ABSOLUTE(.);
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} >sram0_11_seg :sram0_11_phdr
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.NMIExceptionVector.text : ALIGN(4)
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{
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_NMIExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.NMIExceptionVector.text))
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_NMIExceptionVector_text_end = ABSOLUTE(.);
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} >sram0_12_seg :sram0_12_phdr
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.KernelExceptionVector.literal : ALIGN(4)
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{
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_KernelExceptionVector_literal_start = ABSOLUTE(.);
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*(.KernelExceptionVector.literal)
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_KernelExceptionVector_literal_end = ABSOLUTE(.);
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} >sram0_13_seg :sram0_13_phdr
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.KernelExceptionVector.text : ALIGN(4)
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{
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_KernelExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.KernelExceptionVector.text))
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_KernelExceptionVector_text_end = ABSOLUTE(.);
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} >sram0_14_seg :sram0_14_phdr
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.UserExceptionVector.literal : ALIGN(4)
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{
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_UserExceptionVector_literal_start = ABSOLUTE(.);
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*(.UserExceptionVector.literal)
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_UserExceptionVector_literal_end = ABSOLUTE(.);
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} >sram0_15_seg :sram0_15_phdr
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.UserExceptionVector.text : ALIGN(4)
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{
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_UserExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.UserExceptionVector.text))
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_UserExceptionVector_text_end = ABSOLUTE(.);
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} >sram0_16_seg :sram0_16_phdr
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.DoubleExceptionVector.literal : ALIGN(4)
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{
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_DoubleExceptionVector_literal_start = ABSOLUTE(.);
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*(.DoubleExceptionVector.literal)
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_DoubleExceptionVector_literal_end = ABSOLUTE(.);
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} >sram0_17_seg :sram0_17_phdr
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.DoubleExceptionVector.text : ALIGN(4)
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{
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_DoubleExceptionVector_text_start = ABSOLUTE(.);
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KEEP (*(.DoubleExceptionVector.text))
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_DoubleExceptionVector_text_end = ABSOLUTE(.);
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} >sram0_18_seg :sram0_18_phdr
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/* Auto-generated vector linkage, to "vectors" memory region */
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#include <xtensa_vectors.ld>
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>vectors :vectors_phdr
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#define LIB_OBJ_FUNC_IN_SECT(library, obj_file, func) \
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*##library##:##obj_file##(.literal.##func .text.##func) \
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