michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: it8xxx2: introduce SOC_IT8XXX2_PLL_FLASH_48M option

Browse source 
Enable SOC_IT8XXX2_PLL_FLASH_48M at default to reduce latency of
fetching code from flash.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit is contained in:
Dino Li 2021-07-05 14:08:50 +08:00 • committed by Christopher Friedt
commit 7d5411d6e0
6 changed files with 211 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

9
soc/riscv/riscv-ite/common/chip_chipregs.h
View file

@ -1774,6 +1774,15 @@ struct adc_it8xxx2_regs {
#define CGC_OFFSET_SMBB ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08)
#define CGC_OFFSET_SMBA ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04)
/* TODO: rename IT83XX_ECPM_BASE to IT8XXX2_ECPM_BASE */
#define IT8XXX2_ECPM_PLLCTRL ECREG(IT83XX_ECPM_BASE + 0x03)
#ifndef __ASSEMBLER__
enum chip_pll_mode {
CHIP_PLL_DOZE = 0,
CHIP_PLL_SLEEP = 1,
CHIP_PLL_DEEP_DOZE = 3,
};
#endif
#define IT8XXX2_ECPM_AUTOCG ECREG(IT83XX_ECPM_BASE + 0x04)
#define IT8XXX2_ECPM_CGCTRL3R ECREG(IT83XX_ECPM_BASE + 0x05)
#define IT8XXX2_ECPM_PLLFREQR ECREG(IT83XX_ECPM_BASE + 0x06)