michaelh/zephyr
1
0
Fork 0
Code Releases Activity

sys_io: x86: Fix I/O ports bit operations

Browse source 
I/O ports are not memory and thus such asm instruction cannot follow
such constraint. Plus, usual BT* instruction can be used on normal
registers.

Change-Id: Ie3aad668173962a0a90e7cb11231c7843836d412
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka 2015-11-10 17:11:52 +01:00 • committed by Anas Nashif
commit 7cbe13ce3f
1 changed files with 12 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

37
include/arch/x86/asm_inline_gcc.h
View file

@ -304,15 +304,11 @@ static inline __attribute__((always_inline))
{ {
uint32_t reg = 0; uint32_t reg = 0;
__asm__ volatile("inl %%dx, %%eax\n" __asm__ volatile("inl %w1, %0;\n\t"
"mov %1, 1\n" "btsl %2, %0;\n\t"
"shl %%cl, %1\n" "outl %0, %w1;\n\t"
"or %%eax, %1\n"
"outl %%eax, %%dx;\n\t"
: :
: "d" (port), : "a" (reg), "Nd" (port), "Ir" (bit));
"r" (reg), "d" (bit)
: "memory", "cc");
} }
static inline __attribute__((always_inline)) static inline __attribute__((always_inline))
@ -320,15 +316,11 @@ static inline __attribute__((always_inline))
{ {
uint32_t reg = 0; uint32_t reg = 0;
__asm__ volatile("inl %%dx, %%eax\n" __asm__ volatile("inl %w1, %0;\n\t"
"mov %1, 1\n" "btrl %2, %0;\n\t"
"shl %%cl, %1\n" "outl %0, %w1;\n\t"
"and %%eax, %1\n"
"outl %%eax, %%dx;\n\t"
: :
: "d" (port), : "a" (reg), "Nd" (port), "Ir" (bit));
"r" (reg), "d" (bit)
: "memory", "cc");
} }
static inline __attribute__((always_inline)) static inline __attribute__((always_inline))
@ -336,15 +328,10 @@ static inline __attribute__((always_inline))
{ {
uint32_t ret; uint32_t ret;
__asm__ volatile("inl %%dx, %%eax\n" __asm__ volatile("inl %w1, %0\n\t"
"bt %2, %%eax\n" "btl %2, %0\n\t"
"lahf\n" : "=a" (ret)
"mov %1, %%eax\n" : "Nd" (port), "Ir" (bit));
"clc;\n\t"
: "=r" (ret)
: "d" (port),
"Mr" (bit)
: "memory", "cc");
return (ret & 1); return (ret & 1);
} }