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spi: spi_ll_stm32: Add support for STM32F0

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Add support for STM32F0 similar to STM32F3 and STM32L4

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong 2017-09-11 15:01:44 +02:00 • committed by Anas Nashif
commit 7caa56f608
2 changed files with 15 additions and 4 deletions
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8
drivers/spi/Kconfig
View file

@ -54,11 +54,17 @@ config SPI_STM32
bool bool
prompt "STM32 MCU SPI controller driver" prompt "STM32 MCU SPI controller driver"
depends on SPI && SOC_FAMILY_STM32 depends on SPI && SOC_FAMILY_STM32
depends on SOC_SERIES_STM32L4X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F3X depends on SOC_SERIES_STM32L4X || SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X
default n default n
help help
Enable SPI support on the STM32 family of processors. Enable SPI support on the STM32 family of processors.
config SPI_STM32_HAS_FIFO
bool
depends on SPI_STM32
depends on SOC_SERIES_STM32L4X || SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X
default y
config SPI_STM32_INTERRUPT config SPI_STM32_INTERRUPT
bool bool
prompt "STM32 MCU SPI Interrupt Support" prompt "STM32 MCU SPI Interrupt Support"

11
drivers/spi/spi_ll_stm32.c
View file

@ -171,7 +171,7 @@ static void spi_stm32_complete(struct spi_stm32_data *data, SPI_TypeDef *spi,
spi_context_cs_control(&data->ctx, false); spi_context_cs_control(&data->ctx, false);
#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F3X) #if defined(CONFIG_SPI_STM32_HAS_FIFO)
/* Flush RX buffer */ /* Flush RX buffer */
while (LL_SPI_IsActiveFlag_RXNE(spi)) { while (LL_SPI_IsActiveFlag_RXNE(spi)) {
(void) LL_SPI_ReceiveData8(spi); (void) LL_SPI_ReceiveData8(spi);
@ -310,7 +310,7 @@ static int spi_stm32_configure(struct spi_config *config)
LL_SPI_SetDataWidth(spi, LL_SPI_DATAWIDTH_16BIT); LL_SPI_SetDataWidth(spi, LL_SPI_DATAWIDTH_16BIT);
} }
#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F3X) #if defined(CONFIG_SPI_STM32_HAS_FIFO)
LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_QUARTER); LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_QUARTER);
#endif #endif
LL_SPI_SetStandard(spi, LL_SPI_PROTOCOL_MOTOROLA); LL_SPI_SetStandard(spi, LL_SPI_PROTOCOL_MOTOROLA);
@ -371,7 +371,7 @@ static int transceive(struct spi_config *config,
spi_context_buffers_setup(&data->ctx, tx_bufs, tx_count, spi_context_buffers_setup(&data->ctx, tx_bufs, tx_count,
rx_bufs, rx_count, 1); rx_bufs, rx_count, 1);
#if defined(CONFIG_SOC_SERIES_STM32L4X) || defined(CONFIG_SOC_SERIES_STM32F3X) #if defined(CONFIG_SPI_STM32_HAS_FIFO)
/* Flush RX buffer */ /* Flush RX buffer */
while (LL_SPI_IsActiveFlag_RXNE(spi)) { while (LL_SPI_IsActiveFlag_RXNE(spi)) {
(void) LL_SPI_ReceiveData8(spi); (void) LL_SPI_ReceiveData8(spi);
@ -467,8 +467,13 @@ static void spi_stm32_irq_config_func_1(struct device *port);
static const struct spi_stm32_config spi_stm32_cfg_1 = { static const struct spi_stm32_config spi_stm32_cfg_1 = {
.spi = (SPI_TypeDef *) SPI1_BASE, .spi = (SPI_TypeDef *) SPI1_BASE,
.pclken = { .pclken = {
#ifdef CONFIG_SOC_SERIES_STM32F0X
.enr = LL_APB1_GRP2_PERIPH_SPI1,
.bus = STM32_CLOCK_BUS_APB1_2
#else
.enr = LL_APB2_GRP1_PERIPH_SPI1, .enr = LL_APB2_GRP1_PERIPH_SPI1,
.bus = STM32_CLOCK_BUS_APB2 .bus = STM32_CLOCK_BUS_APB2
#endif
}, },
#ifdef CONFIG_SPI_STM32_INTERRUPT #ifdef CONFIG_SPI_STM32_INTERRUPT
.irq_config = spi_stm32_irq_config_func_1, .irq_config = spi_stm32_irq_config_func_1,