diff --git a/arch/arm/soc/st_stm32/stm32l4/soc.c b/arch/arm/soc/st_stm32/stm32l4/soc.c
index f3498bdce30..99109cd3973 100644
--- a/arch/arm/soc/st_stm32/stm32l4/soc.c
+++ b/arch/arm/soc/st_stm32/stm32l4/soc.c
@@ -43,7 +43,12 @@ static int stm32l4_init(struct device *arg)
 	irq_unlock(key);
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+	/* At reset, System core clock is set to 4MHz */
+	SystemCoreClock = 4000000;
+#else
 	SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
 
 	return 0;
 }
diff --git a/arch/arm/soc/st_stm32/stm32l4/soc.h b/arch/arm/soc/st_stm32/stm32l4/soc.h
index cb6c5639c34..2b86ce753ce 100644
--- a/arch/arm/soc/st_stm32/stm32l4/soc.h
+++ b/arch/arm/soc/st_stm32/stm32l4/soc.h
@@ -35,6 +35,13 @@
 #include <stm32l4xx_ll_usart.h>
 #endif
 
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+#include <stm32l4xx_ll_utils.h>
+#include <stm32l4xx_ll_bus.h>
+#include <stm32l4xx_ll_rcc.h>
+#include <stm32l4xx_ll_system.h>
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32L4X_SOC_H_ */
diff --git a/arch/arm/soc/st_stm32/stm32l4/soc_gpio.c b/arch/arm/soc/st_stm32/stm32l4/soc_gpio.c
index b7ea73dc0ad..91d757f9b82 100644
--- a/arch/arm/soc/st_stm32/stm32l4/soc_gpio.c
+++ b/arch/arm/soc/st_stm32/stm32l4/soc_gpio.c
@@ -214,8 +214,17 @@ int stm32_gpio_enable_int(int port, int pin)
 	struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
 	uint32_t *reg;
 
+	/* Enable SYSCFG clock */
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+	struct stm32_pclken pclken = {
+		.bus = STM32_CLOCK_BUS_APB2,
+		.enr = LL_APB2_GRP1_PERIPH_SYSCFG
+	};
+	clock_control_on(clk, (clock_control_subsys_t *) &pclken);
+#else
 	clock_control_on(clk, (clock_control_subsys_t *)
 			      STM32L4X_CLOCK_SUBSYS_SYSCFG);
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
 
 	if (pin <= STM32L4X_PIN3) {
 		reg = &syscfg->exticr1;