boards: stm32: blackpill_f411ce: configure clocks using dt

Migrate clock configuration for blackpill_f411ce board
from Kconfig to device tree.

Additionally, enable LSE crystal configuration for blackpill_f411ce.

Signed-off-by: Kalyan Sriram <kalyan@coderkalyan.com>
This commit is contained in:
Kalyan Sriram 2021-04-29 09:27:15 -07:00 committed by Maureen Helm
commit 7c43ac403b
2 changed files with 23 additions and 17 deletions

View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2020 Brian Bradley <brian.bradley.p@gmail.com>
* Copyright (c) 2021 Kalyan Sriram <coder.kalyan@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -115,3 +116,25 @@
pinctrl-0 = <&adc1_in1_pa1>;
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
};
&pll {
div-m = <25>;
mul-n = <192>;
div-p = <2>;
div-q = <4>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(96)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};

View file

@ -2,8 +2,6 @@
CONFIG_SOC_SERIES_STM32F4X=y
CONFIG_SOC_STM32F411XE=y
# 96MHz system clock (highest value to get a precise USB clock should be 96MHz)
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
# Enable MPU
CONFIG_ARM_MPU=y
@ -25,18 +23,3 @@ CONFIG_GPIO=y
# Clock configuration
CONFIG_CLOCK_CONTROL=y
# SYSCLK selection
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
# HSE configuration
CONFIG_CLOCK_STM32_HSE_CLOCK=25000000
# use HSE as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
# Produce 96MHz clock at PLL output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=25
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=192
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
# Produce 48 MHz clock for USB
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1