boards: stm32: blackpill_f411ce: configure clocks using dt
Migrate clock configuration for blackpill_f411ce board from Kconfig to device tree. Additionally, enable LSE crystal configuration for blackpill_f411ce. Signed-off-by: Kalyan Sriram <kalyan@coderkalyan.com>
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2 changed files with 23 additions and 17 deletions
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2020 Brian Bradley <brian.bradley.p@gmail.com>
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* Copyright (c) 2021 Kalyan Sriram <coder.kalyan@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -115,3 +116,25 @@
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pinctrl-0 = <&adc1_in1_pa1>;
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status = "okay";
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};
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&clk_hse {
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clock-frequency = <DT_FREQ_M(25)>;
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status = "okay";
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};
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&pll {
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div-m = <25>;
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mul-n = <192>;
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div-p = <2>;
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div-q = <4>;
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clocks = <&clk_hse>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(96)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <2>;
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apb2-prescaler = <1>;
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};
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@ -2,8 +2,6 @@
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CONFIG_SOC_SERIES_STM32F4X=y
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CONFIG_SOC_STM32F411XE=y
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# 96MHz system clock (highest value to get a precise USB clock should be 96MHz)
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
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# Enable MPU
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CONFIG_ARM_MPU=y
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@ -25,18 +23,3 @@ CONFIG_GPIO=y
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# Clock configuration
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CONFIG_CLOCK_CONTROL=y
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# SYSCLK selection
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# HSE configuration
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CONFIG_CLOCK_STM32_HSE_CLOCK=25000000
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# use HSE as PLL input
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CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
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# Produce 96MHz clock at PLL output
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CONFIG_CLOCK_STM32_PLL_M_DIVISOR=25
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CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=192
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CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
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# Produce 48 MHz clock for USB
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CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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CONFIG_CLOCK_STM32_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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