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arch: arm: aarch32: Create a fpu stack frame

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Grouping the FPU registers together will make adding FPU support for
Cortex-A/R easier later.  It provides the ability to get the sizeof and
offsetof FPU registers easier.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
This commit is contained in:
Bradley Bolen 2022-04-05 09:11:57 -04:00 • committed by Stephanos Ioannidis
commit 7c1e399179
4 changed files with 23 additions and 14 deletions
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12
arch/arm/core/aarch32/fatal.c
View file

@ -25,15 +25,15 @@ static void esf_dump(const z_arch_esf_t *esf)
esf->basic.a4, esf->basic.ip, esf->basic.lr);
LOG_ERR(" xpsr: 0x%08x", esf->basic.xpsr);
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
for (int i = 0; i < ARRAY_SIZE(esf->s); i += 4) {
for (int i = 0; i < ARRAY_SIZE(esf->fpu.s); i += 4) {
LOG_ERR("s[%2d]: 0x%08x s[%2d]: 0x%08x"
" s[%2d]: 0x%08x s[%2d]: 0x%08x",
i, (uint32_t)esf->s[i],
i + 1, (uint32_t)esf->s[i + 1],
i + 2, (uint32_t)esf->s[i + 2],
i + 3, (uint32_t)esf->s[i + 3]);
i, (uint32_t)esf->fpu.s[i],
i + 1, (uint32_t)esf->fpu.s[i + 1],
i + 2, (uint32_t)esf->fpu.s[i + 2],
i + 3, (uint32_t)esf->fpu.s[i + 3]);
}
LOG_ERR("fpscr: 0x%08x", esf->fpscr);
LOG_ERR("fpscr: 0x%08x", esf->fpu.fpscr);
#endif
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
const struct _callee_saved *callee = esf->extra_info.callee;

6
arch/arm/core/offsets/offsets_aarch32.c
View file

@ -61,8 +61,10 @@ GEN_OFFSET_SYM(_basic_sf_t, xpsr);
GEN_ABSOLUTE_SYM(___basic_sf_t_SIZEOF, sizeof(_basic_sf_t));
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
GEN_OFFSET_SYM(_esf_t, s);
GEN_OFFSET_SYM(_esf_t, fpscr);
GEN_OFFSET_SYM(_fpu_sf_t, s);
GEN_OFFSET_SYM(_fpu_sf_t, fpscr);
GEN_ABSOLUTE_SYM(___fpu_t_SIZEOF, sizeof(_fpu_sf_t));
#endif
GEN_ABSOLUTE_SYM(___esf_t_SIZEOF, sizeof(_esf_t));

3
arch/arm/include/kernel_arch_data.h
View file

@ -44,6 +44,9 @@ extern "C" {
typedef struct __esf _esf_t;
typedef struct __basic_sf _basic_sf_t;
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
typedef struct __fpu_sf _fpu_sf_t;
#endif
#ifdef CONFIG_ARM_MPU
struct z_arm_mpu_partition {

16
include/zephyr/arch/arm/aarch32/exc.h
View file

@ -69,6 +69,14 @@ GTEXT(z_arm_exc_exit);
extern "C" {
#endif
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
struct __fpu_sf {
float s[16];
uint32_t fpscr;
uint32_t undefined;
};
#endif
/* Additional register state that is not stacked by hardware on exception
* entry.
*
@ -97,9 +105,7 @@ struct __esf {
uint32_t xpsr;
} basic;
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
float s[16];
uint32_t fpscr;
uint32_t undefined;
struct __fpu_sf fpu;
#endif
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
struct __extra_esf_info extra_info;
@ -113,9 +119,7 @@ struct __esf {
struct __extra_esf_info extra_info;
#endif
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
float s[16];
uint32_t fpscr;
uint32_t undefined;
struct __fpu_sf fpu;
#endif
struct __basic_sf {
sys_define_gpr_with_alias(a1, r0);