arc: Adding EM9D SOC
EM9D is a ARC CPU configuration that can be selected for the ARC EM Starter Kit. The board support for this board will be submitted separately to expidite review. Change-Id: I2c85bdab6ea7bfb257e94e4c72b11b4568dbac19 Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
This commit is contained in:
Chuck Jordan
Anas Nashif
parent
489f42328c
commit
7bfe11b3e1
8 changed files with 546 additions and 0 deletions
8
arch/arc/soc/em9d/Kbuild
Normal file
8
arch/arc/soc/em9d/Kbuild
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
ccflags-y +=-I$(srctree)/arch/arc/soc/
|
||||
ccflags-y +=-I$(srctree)/include
|
||||
ccflags-y +=-I$(srctree)/include/drivers
|
||||
ccflags-y +=-I$(srctree)/drivers
|
||||
|
||||
asflags-y := ${ccflags-y}
|
||||
|
||||
obj-y = soc.o soc_config.o
|
||||
261
arch/arc/soc/em9d/Kconfig.defconfig
Normal file
261
arch/arc/soc/em9d/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,261 @@
|
|||
#
|
||||
# Copyright (c) 2014 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Synopsys, Inc. All rights reserved.
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
|
||||
if SOC_EM9D
|
||||
|
||||
config SOC
|
||||
default em9d
|
||||
|
||||
config NUM_IRQ_PRIO_LEVELS
|
||||
# This processor supports 4 priority levels:
|
||||
# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
|
||||
# TODO: But regular irq nesting is not implemented --
|
||||
# so this must be 2 for now.
|
||||
default 2
|
||||
|
||||
config NUM_REGULAR_IRQ_PRIO_LEVELS
|
||||
# This processor supports 3 Regular Interrupt priority level (1-3).
|
||||
# TODO: But regular irq nesting is not implemented -- so use 1.
|
||||
default 1
|
||||
|
||||
config NUM_IRQS
|
||||
# must be > the highest interrupt number used
|
||||
default 36
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 20000000
|
||||
|
||||
config HARVARD
|
||||
def_bool y
|
||||
|
||||
config FLASH_BASE_ADDRESS
|
||||
default 0x00000000
|
||||
|
||||
config FLASH_SIZE
|
||||
default 0
|
||||
# em9d has no FLASH so size is 0.
|
||||
|
||||
config SRAM_BASE_ADDRESS
|
||||
default 0x00000000 if NSIM
|
||||
default 0x00000000
|
||||
|
||||
config SRAM_SIZE
|
||||
default 0 if NSIM
|
||||
default 0
|
||||
# em9d has no SRAM so size is 0.
|
||||
|
||||
config ICCM_BASE_ADDRESS
|
||||
default 0x00000000
|
||||
|
||||
config ICCM_SIZE
|
||||
default 256
|
||||
|
||||
config DCCM_BASE_ADDRESS
|
||||
default 0x80000000
|
||||
|
||||
config DCCM_SIZE
|
||||
default 128
|
||||
|
||||
if GPIO
|
||||
|
||||
config GPIO_DW
|
||||
def_bool y
|
||||
|
||||
if GPIO_DW
|
||||
|
||||
config GPIO_DW_0
|
||||
def_bool y
|
||||
|
||||
if GPIO_DW_0
|
||||
|
||||
config GPIO_DW_0_NAME
|
||||
default "GPIO_PORTA"
|
||||
|
||||
config GPIO_DW_0_IRQ_PRI
|
||||
default 1
|
||||
|
||||
endif # GPIO_DW_0
|
||||
|
||||
config GPIO_DW_1
|
||||
def_bool y
|
||||
|
||||
if GPIO_DW_1
|
||||
|
||||
config GPIO_DW_1_NAME
|
||||
default "GPIO_PORTB"
|
||||
|
||||
config GPIO_DW_1_IRQ_PRI
|
||||
default 1
|
||||
|
||||
endif # GPIO_DW_1
|
||||
|
||||
config GPIO_DW_2
|
||||
def_bool y
|
||||
|
||||
if GPIO_DW_2
|
||||
|
||||
config GPIO_DW_2_IRQ_PRI
|
||||
default 1
|
||||
|
||||
config GPIO_DW_2_NAME
|
||||
default "GPIO_PORTC"
|
||||
|
||||
endif # GPIO_DW_2
|
||||
|
||||
config GPIO_DW_3
|
||||
def_bool y
|
||||
|
||||
if GPIO_DW_3
|
||||
|
||||
config GPIO_DW_3_IRQ_PRI
|
||||
default 1
|
||||
|
||||
config GPIO_DW_3_NAME
|
||||
default "GPIO_PORTD"
|
||||
|
||||
endif # GPIO_DW_3
|
||||
|
||||
endif # GPIO_DW
|
||||
|
||||
endif # GPIO
|
||||
|
||||
if I2C
|
||||
|
||||
config I2C_CLOCK_SPEED
|
||||
default 100
|
||||
|
||||
config I2C_DW
|
||||
def_bool y
|
||||
|
||||
if I2C_DW
|
||||
|
||||
config I2C_0
|
||||
def_bool y
|
||||
|
||||
if I2C_0
|
||||
|
||||
config I2C_0_NAME
|
||||
default "I2C_0"
|
||||
config I2C_0_DEFAULT_CFG
|
||||
default 0x3
|
||||
config I2C_0_IRQ_PRI
|
||||
default 1
|
||||
|
||||
endif # I2C_0
|
||||
|
||||
config I2C_1
|
||||
def_bool y
|
||||
|
||||
if I2C_1
|
||||
|
||||
config I2C_1_NAME
|
||||
default "I2C_1"
|
||||
config I2C_1_DEFAULT_CFG
|
||||
default 0x3
|
||||
config I2C_1_IRQ_PRI
|
||||
default 1
|
||||
|
||||
endif # I2C_1
|
||||
|
||||
endif # I2C_DW
|
||||
|
||||
endif # I2C
|
||||
|
||||
if UART_NS16550
|
||||
|
||||
config UART_NS16550_PORT_0
|
||||
def_bool n
|
||||
|
||||
if UART_NS16550_PORT_0
|
||||
|
||||
config UART_NS16550_PORT_0_NAME
|
||||
default "UART_0"
|
||||
config UART_NS16550_PORT_0_IRQ_PRI
|
||||
default 1
|
||||
config UART_NS16550_PORT_0_BAUD_RATE
|
||||
default 115200
|
||||
config UART_NS16550_PORT_0_OPTIONS
|
||||
default 0
|
||||
|
||||
endif # UART_NS16550_PORT_0
|
||||
|
||||
config UART_NS16550_PORT_1
|
||||
def_bool y
|
||||
|
||||
if UART_NS16550_PORT_1
|
||||
|
||||
config UART_NS16550_PORT_1_NAME
|
||||
default "UART_1"
|
||||
config UART_NS16550_PORT_1_IRQ_PRI
|
||||
default 1
|
||||
config UART_NS16550_PORT_1_BAUD_RATE
|
||||
default 115200
|
||||
config UART_NS16550_PORT_1_OPTIONS
|
||||
default 0
|
||||
|
||||
endif # UART_NS16550_PORT_1
|
||||
|
||||
endif # UART_NS16550
|
||||
|
||||
if UART_CONSOLE
|
||||
|
||||
config UART_CONSOLE_ON_DEV_NAME
|
||||
default "UART_1"
|
||||
|
||||
endif
|
||||
|
||||
if SPI
|
||||
|
||||
config SPI_DW
|
||||
def_bool y
|
||||
|
||||
if SPI_DW
|
||||
|
||||
config SPI_DW_CLOCK_GATE
|
||||
def_bool n
|
||||
|
||||
config SPI_DW_FIFO_DEPTH
|
||||
default 32
|
||||
|
||||
config SPI_DW_ARC_AUX_REGS
|
||||
def_bool n
|
||||
|
||||
config SPI_0
|
||||
def_bool y
|
||||
|
||||
if SPI_0
|
||||
|
||||
config SPI_0_IRQ_PRI
|
||||
default 0
|
||||
|
||||
endif # SPI_0
|
||||
|
||||
config SPI_1
|
||||
def_bool y
|
||||
|
||||
if SPI_1
|
||||
|
||||
config SPI_1_IRQ_PRI
|
||||
default 0
|
||||
|
||||
endif # SPI_1
|
||||
|
||||
endif # SPI_DW
|
||||
|
||||
endif # SPI
|
||||
|
||||
endif #SOC_EM9D
|
||||
3
arch/arc/soc/em9d/Kconfig.soc
Normal file
3
arch/arc/soc/em9d/Kconfig.soc
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
|
||||
config SOC_EM9D
|
||||
bool "Synopsys ARC EM9D"
|
||||
7
arch/arc/soc/em9d/Makefile
Normal file
7
arch/arc/soc/em9d/Makefile
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
|
||||
arch-cflags = $(call cc-option,-mARCv2EM) \
|
||||
$(call cc-option,-mav2em,) $(call cc-option,-mno-sdata)
|
||||
|
||||
KBUILD_AFLAGS += $(arch-cflags)
|
||||
KBUILD_CFLAGS += $(arch-cflags)
|
||||
KBUILD_CXXFLAGS += $(arch-cflags)
|
||||
40
arch/arc/soc/em9d/linker.ld
Normal file
40
arch/arc/soc/em9d/linker.ld
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Synopsys, Inc. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Linker script for the Synopsys EM Starterkit v2.2 EM9D platform.
|
||||
*/
|
||||
|
||||
/*
|
||||
* ICCM base address and size
|
||||
*
|
||||
* ICCM includes the exception vector table at reset, which is at
|
||||
* the beginning of the region.
|
||||
*/
|
||||
|
||||
/* Instruction Closely Coupled Memory (ICCM) base address and size */
|
||||
#define ICCM_START CONFIG_ICCM_BASE_ADDRESS
|
||||
#define ICCM_SIZE CONFIG_ICCM_SIZE
|
||||
|
||||
/*
|
||||
* DCCM base address and size. DCCM is the data memory.
|
||||
*/
|
||||
/* Data Closely Coupled Memory (DCCM) base address and size */
|
||||
#define DCCM_START CONFIG_DCCM_BASE_ADDRESS
|
||||
#define DCCM_SIZE CONFIG_DCCM_SIZE
|
||||
|
||||
#include <arch/arc/v2/linker_harvard.ld>
|
||||
|
||||
46
arch/arc/soc/em9d/soc.c
Normal file
46
arch/arc/soc/em9d/soc.c
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/* soc.c - system/hardware module for em_starterkit BSP */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2016 Synopsys, Inc. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* This module provides routines to initialize and support board-level hardware
|
||||
* for the ARC EM Starter kit board.
|
||||
*/
|
||||
|
||||
#include <nanokernel.h>
|
||||
#include "soc.h"
|
||||
#include <init.h>
|
||||
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief perform basic hardware initialization
|
||||
*
|
||||
* Hardware initialized:
|
||||
* - interrupt unit
|
||||
*
|
||||
* RETURNS: N/A
|
||||
*/
|
||||
static int em9d_arc_init(struct device *arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
|
||||
_arc_v2_irq_unit_init();
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(em9d_arc_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
|
||||
136
arch/arc/soc/em9d/soc.h
Normal file
136
arch/arc/soc/em9d/soc.h
Normal file
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Synopsys, Inc. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Board configuration macros for EM Starter kit board
|
||||
*
|
||||
* This header file is used to specify and describe board-level
|
||||
* aspects for the target.
|
||||
*/
|
||||
|
||||
#ifndef _BOARD__H_
|
||||
#define _BOARD__H_
|
||||
|
||||
#include <misc/util.h>
|
||||
|
||||
/* default system clock */
|
||||
|
||||
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
|
||||
/* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
|
||||
|
||||
|
||||
/* IRQs */
|
||||
|
||||
#define IRQ_TIMER0 16
|
||||
#define IRQ_TIMER1 17
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <misc/util.h>
|
||||
#include <drivers/rand32.h>
|
||||
|
||||
/* ARCv2 timer 0 configuration settings for the system clock */
|
||||
#ifdef CONFIG_NANOKERNEL
|
||||
#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 20000000 /* 20MHz reference clock */
|
||||
#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
|
||||
#endif /* CONFIG_NANOKERNEL */
|
||||
|
||||
#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
|
||||
#define CONFIG_ARCV2_TIMER0_INT_PRI 0
|
||||
|
||||
#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
|
||||
#define CONFIG_ARCV2_TIMER1_INT_PRI 1
|
||||
|
||||
#define INT_ENABLE_ARC ~(0x00000001 << 8)
|
||||
#define INT_ENABLE_ARC_BIT_POS (8)
|
||||
|
||||
/* I2C */
|
||||
|
||||
/* I2C_0 is on Pmod2 connector */
|
||||
#define I2C_DW_0_BASE_ADDR 0xF0004000
|
||||
#define I2C_DW_0_IRQ 23
|
||||
|
||||
|
||||
/* I2C_1 is on Pmod4 connector */
|
||||
#define I2C_DW_1_BASE_ADDR 0xF0005000
|
||||
#define I2C_DW_1_IRQ 24
|
||||
|
||||
#define I2C_DW_IRQ_FLAGS 0
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_DW_0_BASE_ADDR 0xF0002000 /* GPIO 0 : PORTA */
|
||||
#define GPIO_DW_0_IRQ 22
|
||||
#define GPIO_DW_0_BITS 32
|
||||
#define GPIO_DW_PORT_0_INT_MASK 0 /* n/a */
|
||||
|
||||
#define GPIO_DW_1_BASE_ADDR 0xF000200C /* GPIO 1 : PORTB */
|
||||
#define GPIO_DW_1_IRQ 0 /* can't interrupt */
|
||||
#define GPIO_DW_1_BITS 9 /* 9 LEDs on board */
|
||||
#define GPIO_DW_PORT_1_INT_MASK 0 /* n/a */
|
||||
|
||||
#define GPIO_DW_2_BASE_ADDR 0xF0002018 /* GPIO 2 : PORTC */
|
||||
#define GPIO_DW_2_IRQ 0 /* can't interrupt */
|
||||
#define GPIO_DW_2_BITS 32
|
||||
#define GPIO_DW_PORT_2_INT_MASK 0 /* n/a */
|
||||
|
||||
#define GPIO_DW_3_BASE_ADDR 0xF0002024 /* GPIO 3 : PORTD */
|
||||
#define GPIO_DW_3_IRQ 0 /* can't interrupt */
|
||||
#define GPIO_DW_3_BITS 12
|
||||
#define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */
|
||||
|
||||
/* undef GPIO_DW_IO_ACCESS .. because memory mapped */
|
||||
/* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
|
||||
/* undef CONFIG_GPIO_DW_CLOCK_GATE */
|
||||
/* undef CONFIG_SOC_QUARK_SE_SS */
|
||||
|
||||
/* SPI */
|
||||
|
||||
#define SPI_DW_SPI_CLOCK SYSCLK_DEFAULT_IOSC_HZ
|
||||
|
||||
#define SPI_DW_PORT_0_REGS 0xF0006000
|
||||
#define SPI_DW_PORT_1_REGS 0xF0007000
|
||||
|
||||
#define SPI_DW_PORT_0_IRQ 25
|
||||
#define SPI_DW_PORT_1_IRQ 26
|
||||
|
||||
/*
|
||||
* SPI Chip Select Assignments on EM Starter Kit
|
||||
*
|
||||
* CS0 Pmod6 - pin 1 - J6
|
||||
* CS1 Pmod5 - pin 1 - J5 & Pmod 6 - pin 7 - J6
|
||||
* CS2 Pmod6 - pin 8 - J6
|
||||
* CS3 SDCard (onboard)
|
||||
* CS4 Internal SPI Slave - loopback
|
||||
* CS5 SPI-Flash (onboard)
|
||||
*/
|
||||
|
||||
/*
|
||||
* UART
|
||||
UART0 vector 27 0xF0008000
|
||||
UART1 vector 28 0xF0009000
|
||||
UART2 vector 29 0xF000A000
|
||||
*/
|
||||
#define UART_NS16550_PORT_0_BASE_ADDR 0xF0008000
|
||||
#define UART_NS16550_PORT_0_IRQ 27
|
||||
#define UART_NS16550_PORT_0_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
|
||||
|
||||
#define UART_NS16550_PORT_1_BASE_ADDR 0xF0009000
|
||||
#define UART_NS16550_PORT_1_IRQ 28
|
||||
#define UART_NS16550_PORT_1_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _BOARD__H_ */
|
||||
45
arch/arc/soc/em9d/soc_config.c
Normal file
45
arch/arc/soc/em9d/soc_config.c
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Synopsys, Inc. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include <device.h>
|
||||
#include <init.h>
|
||||
#include "soc.h"
|
||||
|
||||
|
||||
#ifdef CONFIG_UART_NS16550
|
||||
|
||||
static int uart_ns16550_init(struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
/* On ARC EM Starter kit board,
|
||||
* send the UART the command to clear the interrupt
|
||||
*/
|
||||
#ifdef CONFIG_UART_NS16550_PORT_0
|
||||
sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x4);
|
||||
sys_write32(0, UART_NS16550_PORT_0_BASE_ADDR+0x10);
|
||||
#endif /* CONFIG_UART_NS16550_PORT_0 */
|
||||
#ifdef CONFIG_UART_NS16550_PORT_1
|
||||
sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x4);
|
||||
sys_write32(0, UART_NS16550_PORT_1_BASE_ADDR+0x10);
|
||||
#endif /* CONFIG_UART_NS16550_PORT_1 */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(uart_ns16550_init, PRIMARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
|
||||
|
||||
#endif /* CONFIG_UART_NS16550 */
|
||||
Loading…
Add table
Add a link
Reference in a new issue