boards: xtensa: Add esp32_ethernet_kit board
Adds support for the esp32_ethernet_kit board. esp32_ethernet_kit board is useful for testing ESP32 Ethernet Signed-off-by: Grant Ramsay <grant.ramsay@hotmail.com>
This commit is contained in:
Grant Ramsay
Anas Nashif
parent
9ec0116ce3
commit
7bc8211aa4
17 changed files with 753 additions and 1 deletions
8
boards/xtensa/esp32_ethernet_kit/Kconfig.board
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boards/xtensa/esp32_ethernet_kit/Kconfig.board
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# ESP32-ETHERNET-KIT board configuration
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# Copyright (c) 2022 Grant Ramsay <grant.ramsay@hotmail.com>
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_ESP32_ETHERNET_KIT
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bool "ESP32-ETHERNET-KIT Development Board"
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depends on SOC_ESP32
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boards/xtensa/esp32_ethernet_kit/Kconfig.defconfig
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boards/xtensa/esp32_ethernet_kit/Kconfig.defconfig
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# ESP32-ETHERNET-KIT board configuration
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# Copyright (c) 2022 Grant Ramsay <grant.ramsay@hotmail.com>
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# SPDX-License-Identifier: Apache-2.0
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config BOARD
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default "esp32_ethernet_kit"
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depends on BOARD_ESP32_ETHERNET_KIT
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config ENTROPY_ESP32_RNG
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default y if ENTROPY_GENERATOR
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config ESP_SPIRAM
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default y
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choice SPIRAM_TYPE
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default SPIRAM_TYPE_ESPPSRAM64
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endchoice
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if BT
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config HEAP_MEM_POOL_SIZE
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default 16384
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config ENTROPY_GENERATOR
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default y
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choice BT_HCI_BUS_TYPE
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default BT_ESP32
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endchoice
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endif # BT
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9
boards/xtensa/esp32_ethernet_kit/board.cmake
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boards/xtensa/esp32_ethernet_kit/board.cmake
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# SPDX-License-Identifier: Apache-2.0
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if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
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set(OPENOCD OPENOCD-NOTFOUND)
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endif()
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find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
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include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
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boards/xtensa/esp32_ethernet_kit/doc/index.rst
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boards/xtensa/esp32_ethernet_kit/doc/index.rst
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.. _esp32_ethernet_kit:
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ESP32-ETHERNET-KIT
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##################
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The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables
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Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide
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more flexible power supply options, the ESP32-Ethernet-Kit also supports power
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over Ethernet (PoE).
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.. _get-started-esp32-ethernet-kit-v1.2-overview:
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.. figure:: img/esp32-ethernet-kit-v1.2-overview.jpg
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:align: center
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:alt: ESP32-Ethernet-Kit V1.2
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:figclass: align-center
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ESP32-Ethernet-Kit V1.2 Overview
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Overview
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--------
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ESP32-Ethernet-Kit is an ESP32-based development board produced by
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`Espressif <https://espressif.com>`_.
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It consists of two development boards, the Ethernet board A and the PoE
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board B. The `Ethernet board (A)`_ contains Bluetooth/Wi-Fi dual-mode
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ESP32-WROVER-E module and IP101GRI, a Single Port 10/100 Fast Ethernet
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Transceiver (PHY). The `PoE board (B)`_ provides power over Ethernet
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functionality. The A board can work independently, without the board B
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installed.
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.. _get-started-esp32-ethernet-kit-v1.2:
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.. figure:: img/esp32-ethernet-kit-v1.2.jpg
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:align: center
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:alt: ESP32-Ethernet-Kit V1.2
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:figclass: align-center
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ESP32-Ethernet-Kit V1.2
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For the application loading and monitoring, the Ethernet board (A) also
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features FTDI FT2232H chip - an advanced multi-interface USB bridge.
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This chip enables to use JTAG for direct debugging of ESP32 through the
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USB interface without a separate JTAG debugger.
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Functionality Overview
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----------------------
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The block diagram below shows the main components of ESP32-Ethernet-Kit
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and their interconnections.
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.. figure:: img/esp32-ethernet-kit-v1.1-block-diagram.jpg
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:align: center
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:alt: ESP32-Ethernet-Kit block diagram
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:figclass: align-center
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ESP32-Ethernet-Kit block diagram
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Functional Description
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----------------------
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The following figures and tables describe the key components, interfaces,
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and controls of the ESP32-Ethernet-Kit.
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.. _get-started-esp32-ethernet-kit-a-v1.2-layout:
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Ethernet Board (A)
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^^^^^^^^^^^^^^^^^^
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.. figure:: img/esp32-ethernet-kit-a-v1.2-layout.jpg
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:align: center
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:alt: ESP32-Ethernet-Kit V1.2
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:figclass: align-center
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ESP32-Ethernet-Kit - Ethernet board (A) layout
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The table below provides description starting from the picture's top right
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corner and going clockwise.
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.. list-table:: Table 1 Component Description
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:widths: 40 150
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:header-rows: 1
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* - Key Component
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- Description
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* - ESP32-WROVER-E
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- This ESP32 module features 64-Mbit PSRAM for flexible extended storage
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and data processing capabilities.
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* - GPIO Header 2
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- Five unpopulated through-hole solder pads to provide access to selected
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GPIOs of ESP32. For details, see `GPIO Header 2`_.
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* - Function Switch
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- A 4-bit DIP switch used to configure the functionality of selected GPIOs
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of ESP32. For details see `Function Switch`_.
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* - Tx/Rx LEDs
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- Two LEDs to show the status of UART transmission.
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* - FT2232H
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- The FT2232H chip serves as a multi-protocol USB-to-serial bridge which
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can be programmed and controlled via USB to provide communication with
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ESP32. FT2232H also features USB-to-JTAG interface which is available
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on channel A of the chip, while USB-to-serial is on channel B.
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The FT2232H chip enhances user-friendliness in terms of application
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development and debugging. See
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`ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic <https://dl.espressif.com/dl/schematics/SCH_ESP32-Ethernet-Kit_A_V1.2_20200528.pdf>`_.
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* - USB Port
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- USB interface. Power supply for the board as well as the communication
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interface between a computer and the board.
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* - Power Switch
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- Power On/Off Switch. Toggling the switch to **5V0** position powers the
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board on, toggling to **GND** position powers the board off.
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* - 5V Input
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- The 5 V power supply interface can be more convenient when the board is
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operating autonomously (not connected to a computer).
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* - 5V Power On LED
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- This red LED turns on when power is supplied to the board, either from
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USB or 5 V Input.
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* - DC/DC Converter
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- Provided DC 5 V to 3.3 V conversion, output current up to 2 A.
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* - Board B Connectors
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- A pair male and female header pins for mounting the `PoE board (B)`_
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* - IP101GRI (PHY)
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- The physical layer (PHY) connection to the Ethernet cable is
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implemented using the
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`IP101GRI <http://www.bdtic.com/DataSheet/ICplus/IP101G_DS_R01_20121224.pdf>`_
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chip. The connection between PHY and ESP32 is done through the reduced
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media-independent interface (RMII), a variant of the media-independent
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interface `(MII) <https://en.wikipedia.org/wiki/Media-independent_interface>`_
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standard. The PHY supports the IEEE 802.3/802.3u standard of 10/100
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Mbps.
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* - RJ45 Port
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- Ethernet network data transmission port.
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* - Magnetics Module
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- The Magnetics are part of the Ethernet specification to protect against
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faults and transients, including rejection of common mode signals
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between the transceiver IC and the cable. The magnetics also provide
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galvanic isolation between the transceiver and the Ethernet device.
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* - Link/Activity LEDs
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- Two LEDs (green and red) that respectively indicate the "Link" and
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"Activity" statuses of the PHY.
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* - BOOT Button
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- Download button. Holding down **BOOT** and then pressing **EN**
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initiates Firmware Download mode for downloading firmware through the
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serial port.
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* - EN Button
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- Reset button.
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* - GPIO Header 1
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- This header provides six unpopulated through-hole solder pads connected
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to spare GPIOs of ESP32. For details, see `GPIO Header 1`_.
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PoE Board (B)
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^^^^^^^^^^^^^
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This board coverts power delivered over the Ethernet cable (PoE) to provide a
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power supply for the Ethernet board (A). The main components of the PoE board
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(B) are shown on the block diagram under `Functionality Overview`_.
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The PoE board (B) has the following features:
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* Support for IEEE 802.3at
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* Power output: 5 V, 1.4 A
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To take advantage of the PoE functionality the **RJ45 Port** of the Ethernet
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board (A) should be connected with an Ethernet cable to a switch that supports
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PoE. When the Ethernet board (A) detects 5 V power output from the PoE board
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(B), the USB power will be automatically cut off.
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.. figure:: img/esp32-ethernet-kit-b-v1.0-layout.jpg
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:align: center
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:alt: ESP32-Ethernet-Kit - PoE board (B)
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:figclass: align-center
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ESP32-Ethernet-Kit - PoE board (B) layout
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.. list-table:: Table PoE board (B)
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:widths: 40 150
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:header-rows: 1
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* - Key Component
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- Description
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* - Board A Connector
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- Four female (left) and four male (right) header pins for connecting the
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PoE board (B) to `Ethernet board (A)`_. The pins on the left accept
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power coming from a PoE switch. The pins on the right deliver 5 V power
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supply to the Ethernet board (A).
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* - External Power Terminals
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- Optional power supply (26.6 ~ 54 V) to the PoE board (B).
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.. _get-started-esp32-ethernet-kit-v1.2-setup-options:
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Setup Options
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-------------
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This section describes options to configure the ESP32-Ethernet-Kit hardware.
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Function Switch
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^^^^^^^^^^^^^^^
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When in On position, this DIP switch is routing listed GPIOs to FT2232H to
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provide JTAG functionality. When in Off position, the GPIOs may be used for
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other purposes.
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======= ================
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DIP SW GPIO Pin
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======= ================
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1 GPIO13
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2 GPIO12
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3 GPIO15
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4 GPIO14
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======= ================
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RMII Clock Selection
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^^^^^^^^^^^^^^^^^^^^
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The ethernet MAC and PHY under RMII working mode need a common 50 MHz
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reference clock (i.e. RMII clock) that can be provided either externally,
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or generated from internal ESP32 APLL (not recommended).
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.. note::
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For additional information on the RMII clock selection, please refer to
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`ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic <https://dl.espressif.com/dl/schematics/SCH_ESP32-Ethernet-Kit_A_V1.2_20200528.pdf>`_,
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sheet 2, location D2.
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RMII Clock Sourced Externally by PHY
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""""""""""""""""""""""""""""""""""""
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By default, the ESP32-Ethernet-Kit is configured to provide RMII clock for the
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IP101GRI PHY's 50M_CLKO output. The clock signal is generated by the frequency
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multiplication of 25 MHz crystal connected to the PHY. For details, please see
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the figure below.
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.. figure:: img/esp32-ethernet-kit-rmii-clk-from-phy.jpg
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:align: center
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:alt: RMII Clock from IP101GRI PHY
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:figclass: align-center
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RMII Clock from IP101GRI PHY
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Please note that the PHY is reset on power up by pulling the RESET_N signal
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down with a resistor. ESP32 should assert RESET_N high with GPIO5 to enable
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PHY. Only this can ensure the power-up of system. Otherwise ESP32 may enter
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download mode (when the clock signal of REF_CLK_50M is at a high logic level
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during the GPIO0 power-up sampling phase).
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RMII Clock Sourced Internally from ESP32's APLL
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"""""""""""""""""""""""""""""""""""""""""""""""
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Another option is to source the RMII Clock from internal ESP32 APLL, see
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figure below. The clock signal coming from GPIO0 is first inverted, to account
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for transmission line delay, and then supplied to the PHY.
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.. figure:: img/esp32-ethernet-kit-rmii-clk-to-phy.jpg
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:align: center
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:alt: RMII Clock from ESP Internal APLL
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:figclass: align-center
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RMII Clock from ESP Internal APLL
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To implement this option, users need to remove or add some RC components on
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the board. For details please refer to
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`ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic <https://dl.espressif.com/dl/schematics/SCH_ESP32-Ethernet-Kit_A_V1.2_20200528.pdf>`_,
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sheet 2, location D2. Please note that if the APLL is already used for other
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purposes (e.g. I2S peripheral), then you have no choice but use an external
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RMII clock.
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GPIO Allocation
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---------------
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This section describes allocation of ESP32 GPIOs to specific interfaces or
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functions of the ESP32-Ethernet-Kit.
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IP101GRI (PHY) Interface
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^^^^^^^^^^^^^^^^^^^^^^^^
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The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table
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below. Implementation of ESP32-Ethernet-Kit defaults to Reduced
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Media-Independent Interface (RMII).
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==== ================ ===============
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No. ESP32 Pin (MAC) IP101GRI (PHY)
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==== ================ ===============
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*RMII Interface*
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---------------------------------------
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1 GPIO21 TX_EN
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2 GPIO19 TXD[0]
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3 GPIO22 TXD[1]
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4 GPIO25 RXD[0]
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5 GPIO26 RXD[1]
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6 GPIO27 CRS_DV
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7 GPIO0 REF_CLK
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---- ---------------- ---------------
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*Serial Management Interface*
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---------------------------------------
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8 GPIO23 MDC
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9 GPIO18 MDIO
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---- ---------------- ---------------
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*PHY Reset*
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---------------------------------------
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10 GPIO5 Reset_N
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==== ================ ===============
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.. note::
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The allocation of all pins under the ESP32's *RMII Interface* is fixed and
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cannot be changed either through IO MUX or GPIO Matrix. REF_CLK can only
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be selected from GPIO0, GPIO16 or GPIO17 and it can not be changed through
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GPIO Matrix.
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GPIO Header 1
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^^^^^^^^^^^^^
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This header exposes some GPIOs that are not used elsewhere on the
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ESP32-Ethernet-Kit.
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==== ================
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No. ESP32 Pin
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==== ================
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1 GPIO32
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2 GPIO33
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3 GPIO34
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4 GPIO35
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5 GPIO36
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6 GPIO39
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==== ================
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GPIO Header 2
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^^^^^^^^^^^^^
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This header contains GPIOs that may be used for other purposes depending on
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scenarios described in column "Comments".
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==== ========== ====================
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No. ESP32 Pin Comments
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==== ========== ====================
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1 GPIO17 See note 1
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2 GPIO16 See note 1
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3 GPIO4
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4 GPIO2
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5 GPIO13 See note 2
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6 GPIO12 See note 2
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7 GPIO15 See note 2
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8 GPIO14 See note 2
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9 GND Ground
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10 3V3 3.3 V power supply
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==== ========== ====================
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.. note::
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1. The ESP32 pins GPIO16 and GPIO17 are not broken out to the
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ESP32-WROVER-E module and therefore not available for use. If you need
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to use these pins, please solder a module without PSRAM memory inside,
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e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
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2. Functionality depends on the settings of the `Function Switch`_.
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GPIO Allocation Summary
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^^^^^^^^^^^^^^^^^^^^^^^
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.. csv-table::
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:header: ESP32-WROVER-E,IP101GRI,UART,JTAG,GPIO,Comments
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S_VP,,,,IO36,
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S_VN,,,,IO39,
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IO34,,,,IO34,
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IO35,,,,IO35,
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IO32,,,,IO32,
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IO33,,,,IO33,
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IO25,RXD[0],,,,
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IO26,RXD[1],,,,
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IO27,CRS_DV,,,,
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IO14,,,TMS,IO14,
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IO12,,,TDI,IO12,
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IO13,,,TCK,IO13,
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IO15,,,TDO,IO15,
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IO2,,,,IO2,
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IO0,REF_CLK,,,,See note 1
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IO4,,,,IO4,
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IO16,,,,IO16 (NC),See note 2
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IO17,,,,IO17 (NC),See note 2
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IO5,Reset_N,,,,See note 1
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IO18,MDIO,,,,
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IO19,TXD[0],,,,
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IO21,TX_EN,,,,
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RXD0,,RXD,,,
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TXD0,,TXD,,,
|
||||
IO22,TXD[1],,,,
|
||||
IO23,MDC,,,,
|
||||
|
||||
.. note::
|
||||
|
||||
1. To prevent the power-on state of the GPIO0 from being affected by the
|
||||
clock output on the PHY side, the RESET_N signal to PHY defaults to
|
||||
low, turning the clock output off. After power-on you can control
|
||||
RESET_N with GPIO5 to turn the clock output on. See also
|
||||
`RMII Clock Sourced Externally by PHY`_. For PHYs that cannot turn off
|
||||
the clock output through RESET_N, it is recommended to use a crystal
|
||||
module that can be disabled/enabled externally. Similarly like when
|
||||
using RESET_N, the oscillator module should be disabled by default and
|
||||
turned on by ESP32 after power-up. For a reference design please see
|
||||
`ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic <https://dl.espressif.com/dl/schematics/SCH_ESP32-Ethernet-Kit_A_V1.2_20200528.pdf>`_.
|
||||
|
||||
2. The ESP32 pins GPIO16 and GPIO17 are not broken out to the
|
||||
ESP32-WROVER-E module and therefore not available for use. If you need
|
||||
to use these pins, please solder a module without PSRAM memory inside,
|
||||
e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
|
||||
|
||||
System requirements
|
||||
-------------------
|
||||
|
||||
Prerequisites
|
||||
-------------
|
||||
|
||||
Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
|
||||
below to retrieve those files.
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
west blobs fetch hal_espressif
|
||||
|
||||
.. note::
|
||||
|
||||
It is recommended running the command above after :file:`west update`.
|
||||
|
||||
Building & Flashing
|
||||
-------------------
|
||||
|
||||
Build and flash applications as usual (see :ref:`build_an_application` and
|
||||
:ref:`application_run` for more details).
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: esp32_ethernet_kit
|
||||
:goals: build
|
||||
|
||||
The usual ``flash`` target will work with the ``esp32_ethernet_kit`` board
|
||||
configuration. Here is an example for the :ref:`hello_world`
|
||||
application.
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: esp32_ethernet_kit
|
||||
:goals: flash
|
||||
|
||||
Open the serial monitor using the following command:
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
west espressif monitor
|
||||
|
||||
After the board has automatically reset and booted, you should see the following
|
||||
message in the monitor:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
|
||||
Hello World! esp32_ethernet_kit
|
||||
|
||||
Debugging
|
||||
---------
|
||||
|
||||
As with much custom hardware, the ESP32 modules require patches to
|
||||
OpenOCD that are not upstreamed yet. Espressif maintains their own fork of
|
||||
the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_
|
||||
|
||||
The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the
|
||||
``-DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>``
|
||||
parameter when building.
|
||||
|
||||
Here is an example for building the :ref:`hello_world` application.
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: esp32_ethernet_kit
|
||||
:goals: build flash
|
||||
:gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
|
||||
|
||||
You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application.
|
||||
|
||||
.. zephyr-app-commands::
|
||||
:zephyr-app: samples/hello_world
|
||||
:board: esp32_ethernet_kit
|
||||
:goals: debug
|
||||
|
||||
Related Documents
|
||||
-----------------
|
||||
|
||||
* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic <https://dl.espressif.com/dl/schematics/SCH_ESP32-Ethernet-Kit_A_V1.2_20200528.pdf>`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit PoE Board (B) Schematic <https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_B_V1.0_20190517.pdf>`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) PCB Layout <https://dl.espressif.com/dl/schematics/PCB_ESP32-Ethernet-Kit_A_V1_2_20190829.pdf>`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit PoE Board (B) PCB Layout <https://dl.espressif.com/dl/schematics/PCB_ESP32-Ethernet-Kit_B_V1_0_20190306.pdf>`_ (PDF)
|
||||
* `ESP32 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_ (PDF)
|
||||
* `ESP32-WROVER-E Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf>`_ (PDF)
|
||||
* `OpenOCD ESP32 <https://github.com/espressif/openocd-esp32/releases>`_
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Grant Ramsay <grant.ramsay@hotmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
|
||||
#include <dt-bindings/pinctrl/esp32-pinctrl.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/esp32-gpio-sigmap.h>
|
||||
|
||||
&pinctrl {
|
||||
|
||||
uart0_default: uart0_default {
|
||||
group1 {
|
||||
pinmux = <UART0_TX_GPIO1>;
|
||||
};
|
||||
group2 {
|
||||
pinmux = <UART0_RX_GPIO3>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
spim2_default: spim2_default {
|
||||
group1 {
|
||||
pinmux = <SPIM2_MISO_GPIO12>,
|
||||
<SPIM2_SCLK_GPIO14>,
|
||||
<SPIM2_CSEL_GPIO15>;
|
||||
};
|
||||
group2 {
|
||||
pinmux = <SPIM2_MOSI_GPIO13>;
|
||||
output-low;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
116
boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.dts
Normal file
116
boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.dts
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Grant Ramsay <grant.ramsay@hotmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include <espressif/esp32.dtsi>
|
||||
#include "esp32_ethernet_kit-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "esp32";
|
||||
compatible = "espressif,esp32";
|
||||
|
||||
aliases {
|
||||
uart-0 = &uart0;
|
||||
watchdog0 = &wdt0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
zephyr,sram = &sram0;
|
||||
zephyr,console = &uart0;
|
||||
zephyr,shell-uart = &uart0;
|
||||
zephyr,flash = &flash0;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
clock-frequency = <ESP32_CLK_CPU_240M>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
clock-frequency = <ESP32_CLK_CPU_240M>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
current-speed = <115200>;
|
||||
pinctrl-0 = <&uart0_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
pinctrl-0 = <&spim2_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&timer0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&timer1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&timer2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&timer3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&trng0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&flash0 {
|
||||
status = "okay";
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* Reserve 60kB for the bootloader */
|
||||
boot_partition: partition@1000 {
|
||||
label = "mcuboot";
|
||||
reg = <0x00001000 0x0000F000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
/* Reserve 1024kB for the application in slot 0 */
|
||||
slot0_partition: partition@10000 {
|
||||
label = "image-0";
|
||||
reg = <0x00010000 0x00100000>;
|
||||
};
|
||||
|
||||
/* Reserve 1024kB for the application in slot 1 */
|
||||
slot1_partition: partition@110000 {
|
||||
label = "image-1";
|
||||
reg = <0x00110000 0x00100000>;
|
||||
};
|
||||
|
||||
/* Reserve 256kB for the scratch partition */
|
||||
scratch_partition: partition@210000 {
|
||||
label = "image-scratch";
|
||||
reg = <0x00210000 0x00040000>;
|
||||
};
|
||||
|
||||
storage_partition: partition@250000 {
|
||||
label = "storage";
|
||||
reg = <0x00250000 0x00006000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
16
boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.yaml
Normal file
16
boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.yaml
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
identifier: esp32_ethernet_kit
|
||||
name: ESP32 ETHERNET KIT
|
||||
type: mcu
|
||||
arch: xtensa
|
||||
toolchain:
|
||||
- zephyr
|
||||
supported:
|
||||
- gpio
|
||||
- watchdog
|
||||
- uart
|
||||
- nvs
|
||||
- pwm
|
||||
testing:
|
||||
ignore_tags:
|
||||
- net
|
||||
- bluetooth
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
CONFIG_XTENSA_RESET_VECTOR=n
|
||||
|
||||
CONFIG_BOARD_ESP32_ETHERNET_KIT=y
|
||||
CONFIG_SOC_ESP32=y
|
||||
|
||||
CONFIG_MAIN_STACK_SIZE=2048
|
||||
|
||||
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000
|
||||
|
||||
CONFIG_CONSOLE=y
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
|
||||
CONFIG_XTENSA_USE_CORE_CRT1=n
|
||||
|
||||
CONFIG_GPIO=y
|
||||
|
||||
CONFIG_GEN_ISR_TABLES=y
|
||||
CONFIG_GEN_IRQ_VECTOR_TABLE=n
|
||||
|
||||
CONFIG_CLOCK_CONTROL=y
|
||||
5
boards/xtensa/esp32_ethernet_kit/support/openocd.cfg
Normal file
5
boards/xtensa/esp32_ethernet_kit/support/openocd.cfg
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
set ESP_RTOS none
|
||||
set ESP32_ONLYCPU 1
|
||||
|
||||
source [find interface/ftdi/esp32_devkitj_v1.cfg]
|
||||
source [find target/esp32.cfg]
|
||||
|
|
@ -15,4 +15,5 @@ tests:
|
|||
sample.smp.pktqueue:
|
||||
tags: introduction
|
||||
filter: (CONFIG_MP_NUM_CPUS > 1)
|
||||
platform_exclude: esp32 esp_wrover_kit heltec_wifi_lora32_v2 odroid_go olimex_esp32_evb
|
||||
platform_exclude: esp32 esp_wrover_kit esp32_ethernet_kit
|
||||
heltec_wifi_lora32_v2 odroid_go olimex_esp32_evb
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue