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interrupt_controller: gic: Support PPIs

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The GIC-400 driver currently only supports SPIs because the (32) offset
for the INTIDs is hard-coded in the driver. At the driver level there is
no really difference between PPIs and SPIs so we can easily extend the
driver to support PPIs as well.

This is useful if we want to add support for the ARM Generic Timers that
use INTIDs in the PPI range.

SPI interrupts are in the range [0-987]. PPI interrupts are in the range
[0-15].

This commit adds interrupt 'type' cell to the GIC device tree binding
and changes the 'irq' cell to use interrupt type-specific index, rather
than a linear IRQ number.

The 'type'+'irq (index)' combo is automatically fixed up into a linear
IRQ number by the scripts/dts/gen_defines.py script.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione 2019-10-18 10:32:24 +01:00 • committed by Ioannis Glaropoulos
commit 7baf3f74a9
4 changed files with 34 additions and 21 deletions
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8
drivers/interrupt_controller/gic-400.c
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@ -133,7 +133,6 @@ static void gic_irq_enable(struct device *dev, unsigned int irq)
{
int int_grp, int_off;
irq += GIC_SPI_INT_BASE;
int_grp = irq / 32;
int_off = irq % 32;
@ -144,7 +143,6 @@ static void gic_irq_disable(struct device *dev, unsigned int irq)
{
int int_grp, int_off;
irq += GIC_SPI_INT_BASE;
int_grp = irq / 32;
int_off = irq % 32;
@ -162,14 +160,12 @@ static void gic_irq_set_priority(struct device *dev,
int int_grp, int_off;
u8_t val;
irq += GIC_SPI_INT_BASE;
/* Set priority */
sys_write8(prio & 0xff, GICD_IPRIORITYRn + irq);
/* Set interrupt type */
int_grp = irq / 4;
int_off = (irq % 4) * 2;
int_off = (irq % 16) * 2;
val = sys_read8(GICD_ICFGRn + int_grp);
val &= ~(GIC_INT_TYPE_MASK << int_off);
@ -193,7 +189,7 @@ static void gic_isr(void *arg)
return;
}
isr_offset = cfg->isr_table_offset + irq - GIC_SPI_INT_BASE;
isr_offset = cfg->isr_table_offset + irq;
gic_isr_handle = _sw_isr_table[isr_offset].isr;
if (gic_isr_handle)