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ite/it8xxx2: add support for jtag debug interface

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If enabled, jtag pins will be configured as debug interface
at chip startup.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit is contained in:
Dino Li 2024-02-22 11:50:08 +08:00 • committed by Carles Cufí
commit 7b9349405c
3 changed files with 50 additions and 0 deletions
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14
soc/ite/ec/common/chip_chipregs.h
View file

@ -48,11 +48,25 @@
/* --- General Control (GCTRL) --- */
#define IT8XXX2_GCTRL_BASE 0x00F02000
#define IT8XXX2_GCTRL_EIDSR ECREG(IT8XXX2_GCTRL_BASE + 0x31)
#define IT8XXX2_GCTRL_PMER3 ECREG(IT8XXX2_GCTRL_BASE + 0x46)
/* RISC-V JTAG Debug Interface Enable */
#define IT8XXX2_GCTRL_JTAGEN BIT(1)
/* RISC-V JTAG Debug Interface Selection */
#define IT8XXX2_GCTRL_JTAGSEL BIT(0)
#define IT8XXX2_GCTRL_JTAG (IT8XXX2_GCTRL_JTAGEN | IT8XXX2_GCTRL_JTAGSEL)
/* --- External GPIO Control (EGPIO) --- */
#define IT8XXX2_EGPIO_BASE 0x00F02100
#define IT8XXX2_EGPIO_EGCR ECREG(IT8XXX2_EGPIO_BASE + 0x04)
#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
#define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01660)
#define IT8XXX2_JTAG_VOLT_SET ECREG(0xF01648)
#elif CONFIG_SOC_IT8XXX2_REG_SET_V1
#define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01610)
#define IT8XXX2_JTAG_VOLT_SET ECREG(0xF016e9)
#endif
/* EGPIO register fields */
/*
* 0x04: External GPIO Control

25
soc/ite/ec/common/vector.S
View file

@ -26,6 +26,31 @@ SECTION_FUNC(vectors, __start)
.option norvc;
#ifdef CONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE
/* Enable JTAG debug interface */
la t0, IT8XXX2_GCTRL_PMER3
lb t1, 0(t0)
ori t1, t1, IT8XXX2_GCTRL_JTAG
sb t1, 0(t0)
la t0, IT8XXX2_JTAG_PINS_BASE
li t1, 0
/* Configure GPIOA0 as TCK function */
sb t1, 0(t0)
/* Configure GPIOA1 as TDI function */
sb t1, 1(t0)
/* Configure GPIOA4 as TDO function */
sb t1, 4(t0)
/* Configure GPIOA5 as TMS function */
sb t1, 5(t0)
/* Configure GPIOA6 as TRST function */
sb t1, 6(t0)
/* I/O voltage is 3.3V */
la t0, IT8XXX2_JTAG_VOLT_SET
sb t1, 0(t0)
#endif
/*
* Set mtvec (Machine Trap-Vector Base-Address Register)
* to _isr_wrapper.

11
soc/ite/ec/it8xxx2/Kconfig
View file

@ -99,6 +99,17 @@ config SOC_IT8XXX2_EC_BUS_24MHZ
The clock_frequency of ite,it8xxx2-i2c node (i2c0, i2c1, and i2c2) will
be fixed at 400KHz.
config SOC_IT8XXX2_JTAG_DEBUG_INTERFACE
bool "JTAG debug interface"
help
If enabled, the below five pins are configured as JTAG debug interface:
- GPIOA0 -> TCK
- GPIOA1 -> TDI
- GPIOA4 -> TDO
- GPIOA5 -> TMS
- GPIOA6 -> TRST
Supported I/O voltage is 3.3V.
choice
prompt "Clock source for PLL reference clock"