From 7b38a5feb9ca83b4bf8f71d36071d3b3f418d2a8 Mon Sep 17 00:00:00 2001 From: Piotr Mienkowski Date: Sun, 17 May 2020 00:41:11 +0200 Subject: [PATCH] drivers/clock_control: stm32: Add AHB3 bus support AHB3 bus support is added for compatible series. Additionaly, fix condition for AHB2 support and fix formatting Signed-off-by: Erwan Gouriou Signed-off-by: Piotr Mienkowski --- drivers/clock_control/clock_stm32_ll_common.c | 69 ++++++++++++++----- 1 file changed, 50 insertions(+), 19 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index 122d6bbb9a4..a047f681ff3 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -71,10 +71,11 @@ static void config_bus_clk_init(LL_UTILS_ClkInitTypeDef *clk_init) clk_init->APB1CLKDivider = apb1_prescaler( CONFIG_CLOCK_STM32_APB1_PRESCALER); -#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X) +#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \ + !defined (CONFIG_SOC_SERIES_STM32G0X) clk_init->APB2CLKDivider = apb2_prescaler( CONFIG_CLOCK_STM32_APB2_PRESCALER); -#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */ +#endif } static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) @@ -95,7 +96,7 @@ static inline int stm32_clock_control_on(const struct device *dev, break; #if defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32L5X) || \ - defined(CONFIG_SOC_SERIES_STM32F4X) && !defined(CONFIG_SOC_STM32F410RX) || \ + defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB2_SUPPORT) || \ defined(CONFIG_SOC_SERIES_STM32F7X) || \ defined(CONFIG_SOC_SERIES_STM32F2X) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \ @@ -103,6 +104,17 @@ static inline int stm32_clock_control_on(const struct device *dev, case STM32_CLOCK_BUS_AHB2: LL_AHB2_GRP1_EnableClock(pclken->enr); break; +#endif /* CONFIG_SOC_SERIES_STM32_* */ +#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ + defined(CONFIG_SOC_SERIES_STM32L5X) || \ + defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB3_SUPPORT) || \ + defined(CONFIG_SOC_SERIES_STM32F7X) || \ + defined(CONFIG_SOC_SERIES_STM32F2X) || \ + defined(CONFIG_SOC_SERIES_STM32WBX) || \ + defined(CONFIG_SOC_SERIES_STM32G4X) + case STM32_CLOCK_BUS_AHB3: + LL_AHB3_GRP1_EnableClock(pclken->enr); + break; #endif /* CONFIG_SOC_SERIES_STM32_* */ case STM32_CLOCK_BUS_APB1: LL_APB1_GRP1_EnableClock(pclken->enr); @@ -120,12 +132,13 @@ static inline int stm32_clock_control_on(const struct device *dev, case STM32_CLOCK_BUS_APB2: LL_APB2_GRP1_EnableClock(pclken->enr); break; -#endif /* CONFIG_SOC_SERIES_STM32F0X */ -#if defined (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X) +#endif +#if defined (CONFIG_SOC_SERIES_STM32L0X) || \ + defined (CONFIG_SOC_SERIES_STM32G0X) case STM32_CLOCK_BUS_IOP: LL_IOP_GRP1_EnableClock(pclken->enr); break; -#endif /* CONFIG_SOC_SERIES_STM32L0X || CONFIG_SOC_SERIES_STM32G0X */ +#endif default: return -ENOTSUP; } @@ -147,7 +160,7 @@ static inline int stm32_clock_control_off(const struct device *dev, break; #if defined(CONFIG_SOC_SERIES_STM32L4X) || \ defined(CONFIG_SOC_SERIES_STM32L5X) || \ - defined(CONFIG_SOC_SERIES_STM32F4X) && !defined(CONFIG_SOC_STM32F410RX) || \ + defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB2_SUPPORT) || \ defined(CONFIG_SOC_SERIES_STM32F7X) || \ defined(CONFIG_SOC_SERIES_STM32F2X) || \ defined(CONFIG_SOC_SERIES_STM32WBX) || \ @@ -155,6 +168,17 @@ static inline int stm32_clock_control_off(const struct device *dev, case STM32_CLOCK_BUS_AHB2: LL_AHB2_GRP1_DisableClock(pclken->enr); break; +#endif /* CONFIG_SOC_SERIES_STM32_* */ +#if defined(CONFIG_SOC_SERIES_STM32L4X) || \ + defined(CONFIG_SOC_SERIES_STM32L5X) || \ + defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB3_SUPPORT) || \ + defined(CONFIG_SOC_SERIES_STM32F7X) || \ + defined(CONFIG_SOC_SERIES_STM32F2X) || \ + defined(CONFIG_SOC_SERIES_STM32WBX) || \ + defined(CONFIG_SOC_SERIES_STM32G4X) + case STM32_CLOCK_BUS_AHB3: + LL_AHB3_GRP1_EnableClock(pclken->enr); + break; #endif /* CONFIG_SOC_SERIES_STM32_* */ case STM32_CLOCK_BUS_APB1: LL_APB1_GRP1_DisableClock(pclken->enr); @@ -172,12 +196,13 @@ static inline int stm32_clock_control_off(const struct device *dev, case STM32_CLOCK_BUS_APB2: LL_APB2_GRP1_DisableClock(pclken->enr); break; -#endif /* CONFIG_SOC_SERIES_STM32F0X */ -#if defined (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X) +#endif +#if defined (CONFIG_SOC_SERIES_STM32L0X) || \ + defined (CONFIG_SOC_SERIES_STM32G0X) case STM32_CLOCK_BUS_IOP: LL_IOP_GRP1_DisableClock(pclken->enr); break; -#endif /* CONFIG_SOC_SERIES_STM32L0X || CONFIG_SOC_SERIES_STM32G0X */ +#endif default: return -ENOTSUP; } @@ -200,19 +225,22 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, uint32_t ahb_clock = SystemCoreClock; uint32_t apb1_clock = get_bus_clock(ahb_clock, CONFIG_CLOCK_STM32_APB1_PRESCALER); -#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X) +#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \ + !defined (CONFIG_SOC_SERIES_STM32G0X) uint32_t apb2_clock = get_bus_clock(ahb_clock, CONFIG_CLOCK_STM32_APB2_PRESCALER); -#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */ +#endif ARG_UNUSED(clock); switch (pclken->bus) { case STM32_CLOCK_BUS_AHB1: case STM32_CLOCK_BUS_AHB2: -#if defined (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X) + case STM32_CLOCK_BUS_AHB3: +#if defined (CONFIG_SOC_SERIES_STM32L0X) || \ + defined (CONFIG_SOC_SERIES_STM32G0X) case STM32_CLOCK_BUS_IOP: -#endif /* (CONFIG_SOC_SERIES_STM32L0X) || defined (CONFIG_SOC_SERIES_STM32G0X) */ +#endif *rate = ahb_clock; break; case STM32_CLOCK_BUS_APB1: @@ -232,11 +260,12 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, #endif /* CONFIG_SOC_SERIES_STM32G0X */ *rate = apb1_clock; break; -#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X) +#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \ + !defined (CONFIG_SOC_SERIES_STM32G0X) case STM32_CLOCK_BUS_APB2: *rate = apb2_clock; break; -#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */ +#endif default: return -ENOTSUP; } @@ -450,9 +479,10 @@ static int stm32_clock_control_init(const struct device *dev) /* Set APB1 & APB2 prescaler*/ LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider); -#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X) +#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \ + !defined (CONFIG_SOC_SERIES_STM32G0X) LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider); -#endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */ +#endif /* If freq not increased, set flash latency after all clock setting */ if (new_hclk_freq <= old_hclk_freq) { @@ -543,7 +573,8 @@ static int stm32_clock_control_init(const struct device *dev) /* Set APB1 & APB2 prescaler*/ LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider); -#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X) +#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \ + !defined (CONFIG_SOC_SERIES_STM32G0X) LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider); #endif /* CONFIG_SOC_SERIES_STM32F0X && CONFIG_SOC_SERIES_STM32G0X */