From 7b09d031fae3969fbe8647a57190f1fa21fabd8e Mon Sep 17 00:00:00 2001 From: Felipe Neves Date: Mon, 14 Jun 2021 11:10:47 -0300 Subject: [PATCH] arch: riscv: added support for custom initialization of gp register Plus added implementation for esp32c3 SoC. Signed-off-by: Felipe Neves Signed-off-by: Felipe Neves --- arch/riscv/Kconfig | 6 ++++++ arch/riscv/core/thread.c | 4 ++++ soc/riscv/esp32c3/soc.c | 6 ++++++ soc/riscv/esp32c3/soc.h | 2 ++ 4 files changed, 18 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index cdb5ec7d93c..ec5a7e4526a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -90,6 +90,12 @@ config RISCV_SOC_INTERRUPT_INIT Enable SOC-based interrupt initialization (call soc_interrupt_init, within _IntLibInit when enabled) +config RISCV_SOC_INIT_GP_VALUE + bool "Enable SOC-based global pointer register initialization" + help + Enable SOC-based pointer register initialization + (call __soc_get_gp_initial_value when initializing a thread) + config RISCV_GENERIC_TOOLCHAIN bool "Compile using generic riscv32 toolchain" default y diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c index 9ad30a4b223..cc066f27f90 100644 --- a/arch/riscv/core/thread.c +++ b/arch/riscv/core/thread.c @@ -47,6 +47,10 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, stack_init->a2 = (ulong_t)p2; stack_init->a3 = (ulong_t)p3; +#ifdef CONFIG_RISCV_SOC_INIT_GP_VALUE + stack_init->gp = __soc_get_gp_initial_value(); +#endif + #ifdef CONFIG_THREAD_LOCAL_STORAGE stack_init->tp = (ulong_t)thread->tls; #endif diff --git a/soc/riscv/esp32c3/soc.c b/soc/riscv/esp32c3/soc.c index 9ae5b8b0bea..8139ba59847 100644 --- a/soc/riscv/esp32c3/soc.c +++ b/soc/riscv/esp32c3/soc.c @@ -181,3 +181,9 @@ int arch_irq_is_enabled(unsigned int irq) { return (esprv_intc_get_interrupt_unmask() & (1 << irq)); } + +ulong_t __soc_get_gp_initial_value(void) +{ + extern uint32_t __global_pointer$; + return (ulong_t)&__global_pointer$; +} diff --git a/soc/riscv/esp32c3/soc.h b/soc/riscv/esp32c3/soc.h index 03c31d2b092..f7194e899ef 100644 --- a/soc/riscv/esp32c3/soc.h +++ b/soc/riscv/esp32c3/soc.h @@ -41,6 +41,8 @@ extern STATUS esp32c3_rom_uart_tx_one_char(uint8_t chr); extern STATUS esp32c3_rom_uart_rx_one_char(uint8_t *chr); extern void esp32c3_rom_ets_set_user_start(uint32_t start); +ulong_t __soc_get_gp_initial_value(void); + #endif /* _ASMLANGUAGE */ #endif /* __SOC_H__ */