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drivers/watchdog: stm32: move driver to dts based configuration

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STM32 watchdog driver is now configured from device tree settings.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2019-02-01 14:52:38 +01:00 • committed by Anas Nashif
commit 7ae381a808
10 changed files with 15 additions and 3 deletions
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2
soc/arm/st_stm32/stm32f0/dts_fixup.h
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@ -177,4 +177,6 @@
#define DT_TIM_STM32_17_CLOCK_BITS DT_ST_STM32_TIMERS_40014800_CLOCK_BITS
#define DT_TIM_STM32_17_CLOCK_BUS DT_ST_STM32_TIMERS_40014800_CLOCK_BUS
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
/* End of SoC Level DTS fixup file */

2
soc/arm/st_stm32/stm32f1/dts_fixup.h
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@ -198,4 +198,6 @@
#define DT_TIM_STM32_8_CLOCK_BITS DT_ST_STM32_TIMERS_40013400_CLOCK_BITS
#define DT_TIM_STM32_8_CLOCK_BUS DT_ST_STM32_TIMERS_40013400_CLOCK_BUS
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
/* End of SoC Level DTS fixup file */

2
soc/arm/st_stm32/stm32f2/dts_fixup.h
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@ -138,4 +138,6 @@
#define DT_USB_RAM_SIZE DT_ST_STM32_OTGFS_50000000_RAM_SIZE
#define DT_USB_MAXIMUM_SPEED DT_ST_STM32_OTGFS_50000000_MAXIMUM_SPEED
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
/* End of SoC Level DTS fixup file */

2
soc/arm/st_stm32/stm32f3/dts_fixup.h
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@ -254,4 +254,6 @@
#define DT_RTC_0_IRQ DT_ST_STM32_RTC_40002800_IRQ_0
#define CONFIG_RTC_0_NAME DT_ST_STM32_RTC_40002800_LABEL
#define CONFIG_RTC_PRESCALER DT_ST_STM32_RTC_40002800_PRESCALER
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
/* End of SoC Level DTS fixup file */

1
soc/arm/st_stm32/stm32f4/dts_fixup.h
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@ -366,4 +366,5 @@
#define CONFIG_RTC_0_NAME DT_ST_STM32_RTC_40002800_LABEL
#define CONFIG_RTC_PRESCALER DT_ST_STM32_RTC_40002800_PRESCALER
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
/* End of SoC Level DTS fixup file */

1
soc/arm/st_stm32/stm32f7/dts_fixup.h
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@ -358,4 +358,5 @@
#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F7_FLASH_CONTROLLER_40023C00_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_ST_STM32F7_FLASH_CONTROLLER_40023C00_LABEL
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
/* End of SoC Level DTS fixup file */

1
soc/arm/st_stm32/stm32l0/dts_fixup.h
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@ -126,4 +126,5 @@
#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS
#define DT_USB_RAM_SIZE DT_ST_STM32_USB_40005C00_RAM_SIZE
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
/* End of SoC Level DTS fixup file */

1
soc/arm/st_stm32/stm32l4/dts_fixup.h
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@ -298,4 +298,5 @@
#define DT_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS
#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
/* End of SoC Level DTS fixup file */