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boards: arm: Configure FlexSPI QSPI flash on mimxrt1064_evk

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Enables the FlexSPI NOR flash driver, configures the FlexSPI pins, and
updates the board documentation accordingly on the mimxrt1064_evk.

Note that this SoC has two FlexSPI instances: one instance has an
in-package QSPI flash used for XIP; the other instance has a board-level
QSPI flash used for storage, not XIP. This patch enables the flash
driver on the non-XIP flash only.

Tested with:
  - samples/subsys/fs/littlefs
  - samples/drivers/flash_shell

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>

boards: arm: Rename flexspi_qspi to flexspi_nor for mimxrt1064_evk

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm 2020-12-21 09:10:53 -06:00 • committed by Anas Nashif
commit 7ae122dce0
4 changed files with 50 additions and 0 deletions
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3
boards/arm/mimxrt1064_evk/Kconfig.defconfig
View file

@ -16,6 +16,9 @@ config DISK_ACCESS_USDHC1
default y default y
depends on DISK_ACCESS_USDHC depends on DISK_ACCESS_USDHC
config FLASH_MCUX_FLEXSPI_NOR
default y if FLASH
config I2C config I2C
default y if KSCAN default y if KSCAN

14
boards/arm/mimxrt1064_evk/doc/index.rst
View file

@ -219,6 +219,20 @@ The MIMXRT1064 SoC has four pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+ +---------------+-----------------+---------------------------+
| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | | GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card |
+---------------+-----------------+---------------------------+ +---------------+-----------------+---------------------------+
| GPIO_SD_B1_05 | FLEXSPIA_DQS | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_06 | FLEXSPIA_SS0_B | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_07 | FLEXSPIA_SCLK | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_08 | FLEXSPIA_DATA00 | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_09 | FLEXSPIA_DATA01 | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_10 | FLEXSPIA_DATA02 | QSPI Flash |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_11 | FLEXSPIA_DATA03 | QSPI Flash |
+---------------+-----------------+---------------------------+
System Clock System Clock
============ ============

15
boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts
View file

@ -133,6 +133,10 @@ arduino_i2c: &lpi2c1 {};
}; };
&flexspi { &flexspi {
status = "okay";
ahb-prefetch;
ahb-read-addr-opt;
rx-clock-source = <1>;
reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
is25wp064: is25wp064@0 { is25wp064: is25wp064@0 {
compatible = "nxp,imx-flexspi-nor"; compatible = "nxp,imx-flexspi-nor";
@ -142,6 +146,17 @@ arduino_i2c: &lpi2c1 {};
spi-max-frequency = <133000000>; spi-max-frequency = <133000000>;
status = "okay"; status = "okay";
jedec-id = [9d 70 17]; jedec-id = [9d 70 17];
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage";
reg = <0x00000000 DT_SIZE_M(8)>;
};
};
}; };
}; };

18
boards/arm/mimxrt1064_evk/pinmux.c
View file

@ -301,6 +301,24 @@ static int mimxrt1064_evk_init(const struct device *dev)
imxrt_usdhc_pinmux_cb_register(mimxrt1064_evk_usdhc_pinmux); imxrt_usdhc_pinmux_cb_register(mimxrt1064_evk_usdhc_pinmux);
#endif #endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay) && CONFIG_FLASH
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0x10F1U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0x10F1U);
#endif
return 0; return 0;
} }