soc: nordic: Refactor soc_secure.h
The soc_secure_* function are used by the non-secure application to access hardware resources which are mapped as secure. Using these functions for hardware resources mapped as non-secure is missleading. We have some soc_secure_* functions which read FICR values. In nRF91 and nRF53 platforms this made sense since FICR has hardware fixed mapping as secure. For nRF54 though the FICR has hardware fixed mapping as non-secure. This change refactors the soc_secure.h to exclude the functions which read FICR values from being included when FICR is mapped as non-secure. Also updates the hwinfo and ieee802154 drivers to adjust to this change. Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
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3 changed files with 46 additions and 19 deletions
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@ -15,6 +15,25 @@ void soc_secure_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_sel_t mcu)
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int soc_secure_mem_read(void *dst, void *src, size_t len);
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#else /* defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */
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#if NRF_GPIO_HAS_SEL
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static inline void soc_secure_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_sel_t mcu)
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{
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nrf_gpio_pin_control_select(pin_number, mcu);
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}
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#endif /* NRF_GPIO_HAS_SEL */
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static inline int soc_secure_mem_read(void *dst, void *src, size_t len)
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{
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(void)memcpy(dst, src, len);
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return 0;
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}
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#endif /* defined CONFIG_TRUSTED_EXECUTION_NONSECURE */
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/* Include these soc_secure_* functions only when the FICR is mapped as secure only */
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#if defined(NRF_FICR_S)
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#if defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
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static inline uint32_t soc_secure_read_xosc32mtrim(void)
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{
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@ -41,31 +60,18 @@ static inline void soc_secure_read_deviceid(uint32_t deviceid[2])
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}
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#else /* defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */
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static inline int soc_secure_mem_read(void *dst, void *src, size_t len)
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{
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(void)memcpy(dst, src, len);
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return 0;
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}
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#if NRF_GPIO_HAS_SEL
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static inline void soc_secure_gpio_pin_mcu_select(uint32_t pin_number,
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nrf_gpio_pin_sel_t mcu)
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{
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nrf_gpio_pin_control_select(pin_number, mcu);
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}
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#endif /* NRF_GPIO_HAS_SEL */
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#if defined(CONFIG_SOC_HFXO_CAP_INTERNAL)
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static inline uint32_t soc_secure_read_xosc32mtrim(void)
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{
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return NRF_FICR->XOSC32MTRIM;
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return NRF_FICR_S->XOSC32MTRIM;
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}
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#endif /* defined(CONFIG_SOC_HFXO_CAP_INTERNAL) */
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static inline void soc_secure_read_deviceid(uint32_t deviceid[2])
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{
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deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR, 0);
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deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR, 1);
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deviceid[0] = nrf_ficr_deviceid_get(NRF_FICR_S, 0);
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deviceid[1] = nrf_ficr_deviceid_get(NRF_FICR_S, 1);
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}
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#endif /* defined CONFIG_TRUSTED_EXECUTION_NONSECURE */
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#endif /* defined(NRF_FICR_S) */
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