From 797b6784bb0059e0f98f6088372ddf5c50da80d3 Mon Sep 17 00:00:00 2001
From: Esteban Valverde <esteban.valverde.vega@intel.com>
Date: Tue, 26 Apr 2022 10:59:56 +0100
Subject: [PATCH] drivers: serial: modify ns16550 to use extended FIFO

Cyclone V SoC FPGA supports 128Byte FIFO for UART communication,
this modification adds a feature to use 128byte FIFO serial UART

Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
---
 drivers/serial/Kconfig.ns16550 | 12 ++++++++++++
 drivers/serial/uart_ns16550.c  |  5 ++++-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/Kconfig.ns16550 b/drivers/serial/Kconfig.ns16550
index 29f25a73e11..c7d5a5bbaf2 100644
--- a/drivers/serial/Kconfig.ns16550
+++ b/drivers/serial/Kconfig.ns16550
@@ -28,12 +28,24 @@ config UART_NS16550_DRV_CMD
 
 	  Says n if not sure.
 
+choice
+	prompt "UART type"
+	default UART_NS16750
+	help
+	  Select UART device type
+
 config UART_NS16750
 	bool "UART 16750 (64-bytes FIFO and auto flow control)"
 	help
 	  This enables support for 64-bytes FIFO and automatic hardware
 	  flow control if UART controller is 16750.
 
+config UART_NS16950
+	bool "UART 16950 (128-bytes FIFO and auto flow control)"
+	help
+	  This enables support for 128-bytes FIFO and automatic hardware flow control.
+endchoice
+
 config UART_NS16550_ACCESS_WORD_ONLY
 	bool "NS16550 only allows word access"
 	help
diff --git a/drivers/serial/uart_ns16550.c b/drivers/serial/uart_ns16550.c
index 0cc7191e413..739b6f2190a 100644
--- a/drivers/serial/uart_ns16550.c
+++ b/drivers/serial/uart_ns16550.c
@@ -89,6 +89,7 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
 #define IIR_MASK  0x07 /* interrupt id bits mask  */
 #define IIR_ID    0x06 /* interrupt ID mask without NIP */
 #define IIR_FE    0xC0 /* FIFO mode enabled */
+#define IIR_CH    0x0C /* Character timeout*/
 
 /* equates for FIFO control register */
 
@@ -447,7 +448,7 @@ static int uart_ns16550_configure(const struct device *dev,
 		uart_cfg.data_bits | uart_cfg.stop_bits | uart_cfg.parity);
 
 	mdc = MCR_OUT2 | MCR_RTS | MCR_DTR;
-#ifdef CONFIG_UART_NS16750
+#if defined(CONFIG_UART_NS16750) || defined(CONFIG_UART_NS16950)
 	if (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RTS_CTS) {
 		mdc |= MCR_AFCE;
 	}
@@ -470,6 +471,8 @@ static int uart_ns16550_configure(const struct device *dev,
 	if ((INBYTE(IIR(dev)) & IIR_FE) == IIR_FE) {
 #ifdef CONFIG_UART_NS16750
 		dev_data->fifo_size = 64;
+#elif defined(CONFIG_UART_NS16950)
+		dev_data->fifo_size = 128;
 #else
 		dev_data->fifo_size = 16;
 #endif