boards: arm64: add support of Renesas Spider S4 A55 board

Add support of 'rcar_spider_s4/r8a779f0/a55' board: minimal dts
and configuration.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>

soc/renesas/rcar/rcar_gen4/CMakeLists.txt

@@ -1,5 +1,11 @@
 # Copyright (c) 2023 IoT.bzh
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_include_directories(.)
-set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
+if(CONFIG_SOC_R8A779F0_R52)
+  zephyr_include_directories(r52)
+  set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
+elseif(CONFIG_SOC_R8A779F0_A55)
+  zephyr_include_directories(a55)
+  zephyr_library_sources_ifdef(CONFIG_ARM_MMU a55/mmu_regions.c)
+  set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")
+endif()

soc/renesas/rcar/rcar_gen4/Kconfig

@@ -1,10 +1,15 @@
 # Copyright (c) 2023 IoT.bzh
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_SERIES_RCAR_GEN4
-	bool
+config SOC_R8A779F0_R52
 	select ARM
 	select CPU_CORTEX_R52
 	select GIC_SINGLE_SECURITY_STATE
 	select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL
 	select ARM_ARCH_TIMER
+
+config SOC_R8A779F0_A55
+	select ARM64
+	select CPU_CORTEX_A55
+	select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL
+	select ARM_ARCH_TIMER

soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0

@@ -1,7 +1,7 @@
 # Copyright (c) 2023 IoT.bzh
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_R8A779F0
+if SOC_SERIES_RCAR_GEN4
 
 config NUM_IRQS
 	default 1216 #960 SPI + 256 LPI
@@ -9,4 +9,4 @@ config NUM_IRQS
 config PINCTRL
 	default y
 
-endif # SOC_R8A779F0
+endif # SOC_SERIES_RCAR_GEN4

soc/renesas/rcar/rcar_gen4/Kconfig.soc

@@ -5,14 +5,20 @@ config SOC_SERIES_RCAR_GEN4
 	bool
 	select SOC_FAMILY_RENESAS_RCAR
 
-config SOC_R8A779F0
+config SOC_R8A779F0_R52
 	bool
 	select SOC_SERIES_RCAR_GEN4
 	help
-	  r8a779f0
+	  r8a779f0 r52
+
+config SOC_R8A779F0_A55
+	bool
+	select SOC_SERIES_RCAR_GEN4
+	help
+	  r8a779f0 a55
 
 config SOC_SERIES
 	default "rcar_gen4" if SOC_SERIES_RCAR_GEN4
 
 config SOC
-	default "r8a779f0" if SOC_R8A779F0
+	default "r8a779f0" if SOC_R8A779F0_R52 || SOC_R8A779F0_A55

soc/renesas/rcar/rcar_gen4/a55/mmu_regions.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright 2023 EPAM Systems
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/arch/arm64/arm_mmu.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
+			      MT_DEVICE_nGnRnE | MT_RW | MT_NS),
+
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
+			      MT_DEVICE_nGnRnE | MT_RW | MT_NS),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};

soc/renesas/rcar/rcar_gen4/r52/pinctrl_soc.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2023 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#ifndef ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_
+#include <zephyr/drivers/pinctrl/pinctrl_rcar_common.h>
+
+#endif /* ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_ */

soc/renesas/rcar/soc.yml

@@ -11,3 +11,6 @@ family:
       - name: rcar_gen4
         socs:
           - name: r8a779f0
+            cpuclusters:
+              - name: r52
+              - name: a55