From 794dc83419911341214d84fe4b5f30542d71d8a6 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Sep 2019 09:01:54 -0500 Subject: [PATCH] ext: hal: cmsis: Update ARM CMSIS headers to version 5.6.0 Origin: ARM CMSIS v5.6.0 License: Apache-2.0 URL: https://github.com/ARM-software/CMSIS_5.git commit: b5f0603d6a584d1724d952fd8b0737458b90d62b Purpose: CMSIS Headers update. Maintained-by: External Signed-off-by: Kumar Gala --- ext/hal/cmsis/Include/cmsis_armcc.h | 31 ++++++++- ext/hal/cmsis/Include/cmsis_armclang.h | 28 ++++++++- ext/hal/cmsis/Include/cmsis_armclang_ltm.h | 29 ++++++++- ext/hal/cmsis/Include/cmsis_compiler.h | 12 ++++ ext/hal/cmsis/Include/cmsis_gcc.h | 73 +++++++++++++++++++++- ext/hal/cmsis/Include/cmsis_iccarm.h | 30 ++++++++- ext/hal/cmsis/Include/cmsis_version.h | 8 +-- ext/hal/cmsis/Include/core_armv81mml.h | 1 + ext/hal/cmsis/Include/core_armv8mbl.h | 3 + ext/hal/cmsis/Include/core_armv8mml.h | 3 + ext/hal/cmsis/Include/core_cm0.h | 3 + ext/hal/cmsis/Include/core_cm0plus.h | 5 +- ext/hal/cmsis/Include/core_cm1.h | 3 + ext/hal/cmsis/Include/core_cm23.h | 3 + ext/hal/cmsis/Include/core_cm3.h | 3 + ext/hal/cmsis/Include/core_cm33.h | 3 + ext/hal/cmsis/Include/core_cm35p.h | 3 + ext/hal/cmsis/Include/core_cm4.h | 3 + ext/hal/cmsis/Include/core_cm7.h | 38 ++++++++++- ext/hal/cmsis/Include/core_sc000.h | 3 + ext/hal/cmsis/Include/core_sc300.h | 59 +++++++++-------- 21 files changed, 293 insertions(+), 51 deletions(-) diff --git a/ext/hal/cmsis/Include/cmsis_armcc.h b/ext/hal/cmsis/Include/cmsis_armcc.h index 174d7440330..59f173ac71b 100644 --- a/ext/hal/cmsis/Include/cmsis_armcc.h +++ b/ext/hal/cmsis/Include/cmsis_armcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.0.5 - * @date 14. December 2018 + * @version V5.1.0 + * @date 08. May 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -104,6 +104,31 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface diff --git a/ext/hal/cmsis/Include/cmsis_armclang.h b/ext/hal/cmsis/Include/cmsis_armclang.h index 6a8867d5741..e917f357a32 100644 --- a/ext/hal/cmsis/Include/cmsis_armclang.h +++ b/ext/hal/cmsis/Include/cmsis_armclang.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.1.0 - * @date 14. March 2019 + * @version V5.2.0 + * @date 08. May 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. @@ -110,7 +110,31 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface diff --git a/ext/hal/cmsis/Include/cmsis_armclang_ltm.h b/ext/hal/cmsis/Include/cmsis_armclang_ltm.h index e4002a3fc4c..feec3240597 100644 --- a/ext/hal/cmsis/Include/cmsis_armclang_ltm.h +++ b/ext/hal/cmsis/Include/cmsis_armclang_ltm.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_armclang_ltm.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V1.0.1 - * @date 19. March 2019 + * @version V1.2.0 + * @date 08. May 2019 ******************************************************************************/ /* * Copyright (c) 2018-2019 Arm Limited. All rights reserved. @@ -110,6 +110,31 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif /* ########################### Core Function Access ########################### */ diff --git a/ext/hal/cmsis/Include/cmsis_compiler.h b/ext/hal/cmsis/Include/cmsis_compiler.h index fdb1a971c6a..adbf296f15a 100644 --- a/ext/hal/cmsis/Include/cmsis_compiler.h +++ b/ext/hal/cmsis/Include/cmsis_compiler.h @@ -123,6 +123,10 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif /* @@ -192,6 +196,10 @@ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif /* @@ -260,6 +268,10 @@ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif #else diff --git a/ext/hal/cmsis/Include/cmsis_gcc.h b/ext/hal/cmsis/Include/cmsis_gcc.h index d86b0a2d5a6..3ddcc58b69f 100644 --- a/ext/hal/cmsis/Include/cmsis_gcc.h +++ b/ext/hal/cmsis/Include/cmsis_gcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file - * @version V5.1.0 - * @date 20. December 2018 + * @version V5.2.0 + * @date 08. May 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -113,7 +113,74 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface diff --git a/ext/hal/cmsis/Include/cmsis_iccarm.h b/ext/hal/cmsis/Include/cmsis_iccarm.h index 20b50ce380d..12d68fd9a63 100644 --- a/ext/hal/cmsis/Include/cmsis_iccarm.h +++ b/ext/hal/cmsis/Include/cmsis_iccarm.h @@ -1,13 +1,14 @@ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.8 - * @date 04. September 2018 + * @version V5.1.0 + * @date 08. May 2019 ******************************************************************************/ //------------------------------------------------------------------------------ // -// Copyright (c) 2017-2018 IAR Systems +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. @@ -110,6 +111,10 @@ #define __ASM __asm #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + #ifndef __INLINE #define __INLINE inline #endif @@ -239,6 +244,25 @@ __packed struct __iar_u32 { uint32_t v; }; #endif #endif +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif #ifndef __ICCARM_INTRINSICS_VERSION__ #define __ICCARM_INTRINSICS_VERSION__ 0 diff --git a/ext/hal/cmsis/Include/cmsis_version.h b/ext/hal/cmsis/Include/cmsis_version.h index 660f612aa31..f2e2746626a 100644 --- a/ext/hal/cmsis/Include/cmsis_version.h +++ b/ext/hal/cmsis/Include/cmsis_version.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_version.h * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 + * @version V5.0.3 + * @date 24. June 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ /* CMSIS Version definitions */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ #endif diff --git a/ext/hal/cmsis/Include/core_armv81mml.h b/ext/hal/cmsis/Include/core_armv81mml.h index db6d9f23638..8441e57fb1b 100644 --- a/ext/hal/cmsis/Include/core_armv81mml.h +++ b/ext/hal/cmsis/Include/core_armv81mml.h @@ -2480,6 +2480,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); } diff --git a/ext/hal/cmsis/Include/core_armv8mbl.h b/ext/hal/cmsis/Include/core_armv8mbl.h index 57d9f663fd3..344dca51483 100644 --- a/ext/hal/cmsis/Include/core_armv8mbl.h +++ b/ext/hal/cmsis/Include/core_armv8mbl.h @@ -1253,7 +1253,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -1552,6 +1554,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); } diff --git a/ext/hal/cmsis/Include/core_armv8mml.h b/ext/hal/cmsis/Include/core_armv8mml.h index 30aab58722f..5ddb8aeda7f 100644 --- a/ext/hal/cmsis/Include/core_armv8mml.h +++ b/ext/hal/cmsis/Include/core_armv8mml.h @@ -2053,7 +2053,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -2345,6 +2347,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); } diff --git a/ext/hal/cmsis/Include/core_cm0.h b/ext/hal/cmsis/Include/core_cm0.h index fcf27578ccf..cafae5a0a73 100644 --- a/ext/hal/cmsis/Include/core_cm0.h +++ b/ext/hal/cmsis/Include/core_cm0.h @@ -624,7 +624,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -831,6 +833,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = 0x0U; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ } diff --git a/ext/hal/cmsis/Include/core_cm0plus.h b/ext/hal/cmsis/Include/core_cm0plus.h index 65ea443095f..d104965db51 100644 --- a/ext/hal/cmsis/Include/core_cm0plus.h +++ b/ext/hal/cmsis/Include/core_cm0plus.h @@ -5,7 +5,7 @@ * @date 13. March 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -742,7 +742,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -953,6 +955,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) uint32_t vectors = 0x0U; #endif (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ } diff --git a/ext/hal/cmsis/Include/core_cm1.h b/ext/hal/cmsis/Include/core_cm1.h index 72c515cb092..76b4569743a 100644 --- a/ext/hal/cmsis/Include/core_cm1.h +++ b/ext/hal/cmsis/Include/core_cm1.h @@ -651,7 +651,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -858,6 +860,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)0x0U; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ } diff --git a/ext/hal/cmsis/Include/core_cm23.h b/ext/hal/cmsis/Include/core_cm23.h index 26fe163a0e8..b79c6af0b1e 100644 --- a/ext/hal/cmsis/Include/core_cm23.h +++ b/ext/hal/cmsis/Include/core_cm23.h @@ -1328,7 +1328,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -1627,6 +1629,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) uint32_t *vectors = (uint32_t *)0x0U; #endif vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); } diff --git a/ext/hal/cmsis/Include/core_cm3.h b/ext/hal/cmsis/Include/core_cm3.h index ea5405088c3..8157ca782da 100644 --- a/ext/hal/cmsis/Include/core_cm3.h +++ b/ext/hal/cmsis/Include/core_cm3.h @@ -1504,7 +1504,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -1729,6 +1731,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = (uint32_t )SCB->VTOR; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ } diff --git a/ext/hal/cmsis/Include/core_cm33.h b/ext/hal/cmsis/Include/core_cm33.h index d5d97a96f2d..7fed59a88e3 100644 --- a/ext/hal/cmsis/Include/core_cm33.h +++ b/ext/hal/cmsis/Include/core_cm33.h @@ -2128,7 +2128,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -2420,6 +2422,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); } diff --git a/ext/hal/cmsis/Include/core_cm35p.h b/ext/hal/cmsis/Include/core_cm35p.h index c00e54ca7a9..5579c823068 100644 --- a/ext/hal/cmsis/Include/core_cm35p.h +++ b/ext/hal/cmsis/Include/core_cm35p.h @@ -2128,7 +2128,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -2420,6 +2422,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); } diff --git a/ext/hal/cmsis/Include/core_cm4.h b/ext/hal/cmsis/Include/core_cm4.h index f205b333f32..12c023b8017 100644 --- a/ext/hal/cmsis/Include/core_cm4.h +++ b/ext/hal/cmsis/Include/core_cm4.h @@ -1680,7 +1680,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -1905,6 +1907,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = (uint32_t )SCB->VTOR; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ } diff --git a/ext/hal/cmsis/Include/core_cm7.h b/ext/hal/cmsis/Include/core_cm7.h index 41f9afb64da..c4515d8fa31 100644 --- a/ext/hal/cmsis/Include/core_cm7.h +++ b/ext/hal/cmsis/Include/core_cm7.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.1.0 - * @date 13. March 2019 + * @version V5.1.1 + * @date 28. March 2019 ******************************************************************************/ /* * Copyright (c) 2009-2019 Arm Limited. All rights reserved. @@ -1903,7 +1903,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -2128,6 +2130,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t vectors = (uint32_t )SCB->VTOR; (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); } @@ -2229,6 +2232,7 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void) #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) #define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ /** \brief Enable I-Cache @@ -2284,6 +2288,36 @@ __STATIC_FORCEINLINE void SCB_InvalidateICache (void) } +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + /** \brief Enable D-Cache \details Turns on D-Cache diff --git a/ext/hal/cmsis/Include/core_sc000.h b/ext/hal/cmsis/Include/core_sc000.h index 389535a7cf2..cf92577b63e 100644 --- a/ext/hal/cmsis/Include/core_sc000.h +++ b/ext/hal/cmsis/Include/core_sc000.h @@ -750,7 +750,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -904,6 +906,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ } diff --git a/ext/hal/cmsis/Include/core_sc300.h b/ext/hal/cmsis/Include/core_sc300.h index 5478ea74a5c..40f3af81bec 100644 --- a/ext/hal/cmsis/Include/core_sc300.h +++ b/ext/hal/cmsis/Include/core_sc300.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.7 - * @date 12. November 2018 + * @version V5.0.8 + * @date 31. May 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -342,7 +342,7 @@ typedef struct __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24U]; __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24U]; + uint32_t RESERVED1[24U]; __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24U]; __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ @@ -653,13 +653,23 @@ typedef struct { uint32_t RESERVED0[1U]; __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + /*@} end of group CMSIS_SCnotSCB */ @@ -739,10 +749,7 @@ typedef struct __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ @@ -793,18 +800,6 @@ typedef struct #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ @@ -1037,13 +1032,13 @@ typedef struct /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ @@ -1066,13 +1061,13 @@ typedef struct /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ @@ -1448,7 +1443,6 @@ typedef struct #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - /** \brief Set Priority Grouping \details Sets the priority grouping field using the required unlock sequence. @@ -1467,7 +1461,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -1493,7 +1487,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -1716,8 +1712,9 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ } @@ -1731,8 +1728,8 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) */ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); }