michaelh/zephyr
1
0
Fork 0
Code Releases Activity

include: arm64: Add BSS align when MPU enabled

Browse source 
When MPU is enabled, the sections need to be 64 bytes aligned.
In the case of MMU, BSS section will be 4k aligned, because the first
variable in BSS section 'base_xlat_table' is explicitly aligned by
'__aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t))'.

However, with MPU, we do not have such a variable. So it's necessary
to fix the alignment of the BSS section in the linker.ld

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
This commit is contained in:
Jaxson Han 2021-03-04 17:59:31 +08:00 • committed by Anas Nashif
commit 794656913b
1 changed files with 8 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

9
include/arch/arm64/scripts/linker.ld
View file

@ -50,11 +50,18 @@
#if defined(CONFIG_ARM_MMU) #if defined(CONFIG_ARM_MMU)
_region_min_align = CONFIG_MMU_PAGE_SIZE; _region_min_align = CONFIG_MMU_PAGE_SIZE;
#elif defined(CONFIG_ARM_MPU)
_region_min_align = CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE;
#define BSS_ALIGN ALIGN(_region_min_align)
#else #else
/* If building without MMU support, use default 4-byte alignment. */ /* If building without MMU support, use default 4-byte alignment. */
_region_min_align = 4; _region_min_align = 4;
#endif #endif
#ifndef BSS_ALIGN
#define BSS_ALIGN
#endif
#define MMU_ALIGN . = ALIGN(_region_min_align) #define MMU_ALIGN . = ALIGN(_region_min_align)
MEMORY MEMORY
@ -223,7 +230,7 @@ SECTIONS
_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME); _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
#endif /* CONFIG_USERSPACE */ #endif /* CONFIG_USERSPACE */
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD), BSS_ALIGN)
{ {
/* /*
* For performance, BSS section is assumed to be 4 byte aligned and * For performance, BSS section is assumed to be 4 byte aligned and