From 792fd57d96327dee3d7477479489ebd9fc42f907 Mon Sep 17 00:00:00 2001 From: Hardeep Sharma Date: Tue, 23 Apr 2024 10:56:32 +0000 Subject: [PATCH] tests: drivers: build_all: Build Altera FPGA driver Altera FPGA driver should be built on a regular basis to ensure that there are no regressions Signed-off-by: Hardeep Sharma --- tests/drivers/build_all/fpga/app.overlay | 12 ++++++++++++ tests/drivers/build_all/fpga/prj.conf | 5 +++++ 2 files changed, 17 insertions(+) diff --git a/tests/drivers/build_all/fpga/app.overlay b/tests/drivers/build_all/fpga/app.overlay index e26db8e7ba7..6135bfa5745 100644 --- a/tests/drivers/build_all/fpga/app.overlay +++ b/tests/drivers/build_all/fpga/app.overlay @@ -38,6 +38,18 @@ #include "spi.dtsi" }; }; + + fpga0: bridges { + compatible = "altr,socfpga-agilex-bridge"; + status = "okay"; + }; + + sip_smc: smc { + compatible = "intel,socfpga-agilex-sip-smc"; + method = "smc"; + status = "okay"; + zephyr,num-clients = <2>; + }; }; /* Put device specific modifications to properties or disabling of devices diff --git a/tests/drivers/build_all/fpga/prj.conf b/tests/drivers/build_all/fpga/prj.conf index 579660e8df1..d6c9a05db52 100644 --- a/tests/drivers/build_all/fpga/prj.conf +++ b/tests/drivers/build_all/fpga/prj.conf @@ -11,3 +11,8 @@ CONFIG_FPGA=y # iCE40 FPGAs on a single bus to 1. CONFIG_PINCTRL=n CONFIG_ICE40_FPGA=y +CONFIG_ALTERA_AGILEX_BRIDGE_FPGA=y +CONFIG_ARM_SIP_SVC_DRIVER=y +CONFIG_ARM_SIP_SVC_SUBSYS=y +CONFIG_ARM_SIP_SVC_SUBSYS_SINGLY_OPEN=y +CONFIG_HEAP_MEM_POOL_SIZE=16384