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drivers: can: mcan: reindent register definitions

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Reindent the Bosch M_CAN register definitions.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit is contained in:
Henrik Brix Andersen 2023-05-26 15:12:53 +02:00 • committed by Anas Nashif
commit 78f956f308
1 changed files with 77 additions and 77 deletions
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154
drivers/can/can_mcan.h
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@ -21,7 +21,7 @@
*/ */
/* Core Release register */ /* Core Release register */
#define CAN_MCAN_CREL 0x000 #define CAN_MCAN_CREL 0x000
#define CAN_MCAN_CREL_REL GENMASK(31, 28) #define CAN_MCAN_CREL_REL GENMASK(31, 28)
#define CAN_MCAN_CREL_STEP GENMASK(27, 24) #define CAN_MCAN_CREL_STEP GENMASK(27, 24)
#define CAN_MCAN_CREL_SUBSTEP GENMASK(23, 20) #define CAN_MCAN_CREL_SUBSTEP GENMASK(23, 20)
@ -30,15 +30,15 @@
#define CAN_MCAN_CREL_DAY GENMASK(7, 0) #define CAN_MCAN_CREL_DAY GENMASK(7, 0)
/* Endian register */ /* Endian register */
#define CAN_MCAN_ENDN 0x004 #define CAN_MCAN_ENDN 0x004
#define CAN_MCAN_ENDN_ETV GENMASK(31, 0) #define CAN_MCAN_ENDN_ETV GENMASK(31, 0)
/* Customer register */ /* Customer register */
#define CAN_MCAN_CUST 0x008 #define CAN_MCAN_CUST 0x008
#define CAN_MCAN_CUST_CUST GENMASK(31, 0) #define CAN_MCAN_CUST_CUST GENMASK(31, 0)
/* Data Bit Timing & Prescaler register */ /* Data Bit Timing & Prescaler register */
#define CAN_MCAN_DBTP 0x00C #define CAN_MCAN_DBTP 0x00C
#define CAN_MCAN_DBTP_TDC BIT(23) #define CAN_MCAN_DBTP_TDC BIT(23)
#define CAN_MCAN_DBTP_DBRP GENMASK(20, 16) #define CAN_MCAN_DBTP_DBRP GENMASK(20, 16)
#define CAN_MCAN_DBTP_DTSEG1 GENMASK(12, 8) #define CAN_MCAN_DBTP_DTSEG1 GENMASK(12, 8)
@ -46,22 +46,22 @@
#define CAN_MCAN_DBTP_DSJW GENMASK(3, 0) #define CAN_MCAN_DBTP_DSJW GENMASK(3, 0)
/* Test register */ /* Test register */
#define CAN_MCAN_TEST 0x010 #define CAN_MCAN_TEST 0x010
#define CAN_MCAN_TEST_SVAL BIT(21) #define CAN_MCAN_TEST_SVAL BIT(21)
#define CAN_MCAN_TEST_TXBNS GENMASK(20, 16) #define CAN_MCAN_TEST_TXBNS GENMASK(20, 16)
#define CAN_MCAN_TEST_PVAL BIT(13) #define CAN_MCAN_TEST_PVAL BIT(13)
#define CAN_MCAN_TEST_TXBNP GENMASK(12, 8) #define CAN_MCAN_TEST_TXBNP GENMASK(12, 8)
#define CAN_MCAN_TEST_RX BIT(7) #define CAN_MCAN_TEST_RX BIT(7)
#define CAN_MCAN_TEST_TX GENMASK(6, 5) #define CAN_MCAN_TEST_TX GENMASK(6, 5)
#define CAN_MCAN_TEST_LBCK BIT(4) #define CAN_MCAN_TEST_LBCK BIT(4)
/* RAM Watchdog register */ /* RAM Watchdog register */
#define CAN_MCAN_RWD 0x014 #define CAN_MCAN_RWD 0x014
#define CAN_MCAN_RWD_WDV GENMASK(15, 8) #define CAN_MCAN_RWD_WDV GENMASK(15, 8)
#define CAN_MCAN_RWD_WDC GENMASK(7, 0) #define CAN_MCAN_RWD_WDC GENMASK(7, 0)
/* CC Control register */ /* CC Control register */
#define CAN_MCAN_CCCR 0x018 #define CAN_MCAN_CCCR 0x018
#define CAN_MCAN_CCCR_NISO BIT(15) #define CAN_MCAN_CCCR_NISO BIT(15)
#define CAN_MCAN_CCCR_TXP BIT(14) #define CAN_MCAN_CCCR_TXP BIT(14)
#define CAN_MCAN_CCCR_EFBI BIT(13) #define CAN_MCAN_CCCR_EFBI BIT(13)
@ -80,81 +80,81 @@
#define CAN_MCAN_CCCR_INIT BIT(0) #define CAN_MCAN_CCCR_INIT BIT(0)
/* Nominal Bit Timing & Prescaler register */ /* Nominal Bit Timing & Prescaler register */
#define CAN_MCAN_NBTP 0x01C #define CAN_MCAN_NBTP 0x01C
#define CAN_MCAN_NBTP_NSJW GENMASK(31, 25) #define CAN_MCAN_NBTP_NSJW GENMASK(31, 25)
#define CAN_MCAN_NBTP_NBRP GENMASK(24, 16) #define CAN_MCAN_NBTP_NBRP GENMASK(24, 16)
#define CAN_MCAN_NBTP_NTSEG1 GENMASK(15, 8) #define CAN_MCAN_NBTP_NTSEG1 GENMASK(15, 8)
#define CAN_MCAN_NBTP_NTSEG2 GENMASK(6, 0) #define CAN_MCAN_NBTP_NTSEG2 GENMASK(6, 0)
/* Timestamp Counter Configuration register */ /* Timestamp Counter Configuration register */
#define CAN_MCAN_TSCC 0x020 #define CAN_MCAN_TSCC 0x020
#define CAN_MCAN_TSCC_TCP GENMASK(19, 16) #define CAN_MCAN_TSCC_TCP GENMASK(19, 16)
#define CAN_MCAN_TSCC_TSS GENMASK(1, 0) #define CAN_MCAN_TSCC_TSS GENMASK(1, 0)
/* Timestamp Counter Value register */ /* Timestamp Counter Value register */
#define CAN_MCAN_TSCV 0x024 #define CAN_MCAN_TSCV 0x024
#define CAN_MCAN_TSCV_TSC GENMASK(15, 0) #define CAN_MCAN_TSCV_TSC GENMASK(15, 0)
/* Timeout Counter Configuration register */ /* Timeout Counter Configuration register */
#define CAN_MCAN_TOCC 0x028 #define CAN_MCAN_TOCC 0x028
#define CAN_MCAN_TOCC_TOP GENMASK(31, 16) #define CAN_MCAN_TOCC_TOP GENMASK(31, 16)
#define CAN_MCAN_TOCC_TOS GENMASK(2, 1) #define CAN_MCAN_TOCC_TOS GENMASK(2, 1)
#define CAN_MCAN_TOCC_ETOC BIT(1) #define CAN_MCAN_TOCC_ETOC BIT(1)
/* Timeout Counter Value register */ /* Timeout Counter Value register */
#define CAN_MCAN_TOCV 0x02C #define CAN_MCAN_TOCV 0x02C
#define CAN_MCAN_TOCV_TOC GENMASK(15, 0) #define CAN_MCAN_TOCV_TOC GENMASK(15, 0)
/* Error Counter register */ /* Error Counter register */
#define CAN_MCAN_ECR 0x040 #define CAN_MCAN_ECR 0x040
#define CAN_MCAN_ECR_CEL GENMASK(23, 16) #define CAN_MCAN_ECR_CEL GENMASK(23, 16)
#define CAN_MCAN_ECR_RP BIT(15) #define CAN_MCAN_ECR_RP BIT(15)
#define CAN_MCAN_ECR_REC GENMASK(14, 8) #define CAN_MCAN_ECR_REC GENMASK(14, 8)
#define CAN_MCAN_ECR_TEC GENMASK(7, 0) #define CAN_MCAN_ECR_TEC GENMASK(7, 0)
/* Protocol Status register */ /* Protocol Status register */
#define CAN_MCAN_PSR 0x044 #define CAN_MCAN_PSR 0x044
#define CAN_MCAN_PSR_TDCV GENMASK(22, 16) #define CAN_MCAN_PSR_TDCV GENMASK(22, 16)
#define CAN_MCAN_PSR_PXE BIT(14) #define CAN_MCAN_PSR_PXE BIT(14)
#define CAN_MCAN_PSR_RFDF BIT(13) #define CAN_MCAN_PSR_RFDF BIT(13)
#define CAN_MCAN_PSR_RBRS BIT(12) #define CAN_MCAN_PSR_RBRS BIT(12)
#define CAN_MCAN_PSR_RESI BIT(11) #define CAN_MCAN_PSR_RESI BIT(11)
#define CAN_MCAN_PSR_DLEC GENMASK(10, 8) #define CAN_MCAN_PSR_DLEC GENMASK(10, 8)
#define CAN_MCAN_PSR_BO BIT(7) #define CAN_MCAN_PSR_BO BIT(7)
#define CAN_MCAN_PSR_EW BIT(6) #define CAN_MCAN_PSR_EW BIT(6)
#define CAN_MCAN_PSR_EP BIT(5) #define CAN_MCAN_PSR_EP BIT(5)
#define CAN_MCAN_PSR_ACT GENMASK(4, 3) #define CAN_MCAN_PSR_ACT GENMASK(4, 3)
#define CAN_MCAN_PSR_LEC GENMASK(2, 0) #define CAN_MCAN_PSR_LEC GENMASK(2, 0)
/* Transmitter Delay Compensation register */ /* Transmitter Delay Compensation register */
#define CAN_MCAN_TDCR 0x048 #define CAN_MCAN_TDCR 0x048
#define CAN_MCAN_TDCR_TDCO GENMASK(14, 8) #define CAN_MCAN_TDCR_TDCO GENMASK(14, 8)
#define CAN_MCAN_TDCR_TDCF GENMASK(6, 0) #define CAN_MCAN_TDCR_TDCF GENMASK(6, 0)
/* Interrupt register */ /* Interrupt register */
#define CAN_MCAN_IR 0x050 #define CAN_MCAN_IR 0x050
#define CAN_MCAN_IR_ARA BIT(29) #define CAN_MCAN_IR_ARA BIT(29)
#define CAN_MCAN_IR_PED BIT(28) #define CAN_MCAN_IR_PED BIT(28)
#define CAN_MCAN_IR_PEA BIT(27) #define CAN_MCAN_IR_PEA BIT(27)
#define CAN_MCAN_IR_WDI BIT(26) #define CAN_MCAN_IR_WDI BIT(26)
#define CAN_MCAN_IR_BO BIT(25) #define CAN_MCAN_IR_BO BIT(25)
#define CAN_MCAN_IR_EW BIT(24) #define CAN_MCAN_IR_EW BIT(24)
#define CAN_MCAN_IR_EP BIT(23) #define CAN_MCAN_IR_EP BIT(23)
#define CAN_MCAN_IR_ELO BIT(22) #define CAN_MCAN_IR_ELO BIT(22)
#define CAN_MCAN_IR_BEU BIT(21) #define CAN_MCAN_IR_BEU BIT(21)
#define CAN_MCAN_IR_BEC BIT(20) #define CAN_MCAN_IR_BEC BIT(20)
#define CAN_MCAN_IR_DRX BIT(19) #define CAN_MCAN_IR_DRX BIT(19)
#define CAN_MCAN_IR_TOO BIT(18) #define CAN_MCAN_IR_TOO BIT(18)
#define CAN_MCAN_IR_MRAF BIT(17) #define CAN_MCAN_IR_MRAF BIT(17)
#define CAN_MCAN_IR_TSW BIT(16) #define CAN_MCAN_IR_TSW BIT(16)
#define CAN_MCAN_IR_TEFL BIT(15) #define CAN_MCAN_IR_TEFL BIT(15)
#define CAN_MCAN_IR_TEFF BIT(14) #define CAN_MCAN_IR_TEFF BIT(14)
#define CAN_MCAN_IR_TEFW BIT(13) #define CAN_MCAN_IR_TEFW BIT(13)
#define CAN_MCAN_IR_TEFN BIT(12) #define CAN_MCAN_IR_TEFN BIT(12)
#define CAN_MCAN_IR_TFE BIT(11) #define CAN_MCAN_IR_TFE BIT(11)
#define CAN_MCAN_IR_TCF BIT(10) #define CAN_MCAN_IR_TCF BIT(10)
#define CAN_MCAN_IR_TC BIT(9) #define CAN_MCAN_IR_TC BIT(9)
#define CAN_MCAN_IR_HPM BIT(8) #define CAN_MCAN_IR_HPM BIT(8)
#define CAN_MCAN_IR_RF1L BIT(7) #define CAN_MCAN_IR_RF1L BIT(7)
#define CAN_MCAN_IR_RF1F BIT(6) #define CAN_MCAN_IR_RF1F BIT(6)
#define CAN_MCAN_IR_RF1W BIT(5) #define CAN_MCAN_IR_RF1W BIT(5)
@ -165,14 +165,14 @@
#define CAN_MCAN_IR_RF0N BIT(0) #define CAN_MCAN_IR_RF0N BIT(0)
/* Interrupt Enable register */ /* Interrupt Enable register */
#define CAN_MCAN_IE 0x054 #define CAN_MCAN_IE 0x054
#define CAN_MCAN_IE_ARAE BIT(29) #define CAN_MCAN_IE_ARAE BIT(29)
#define CAN_MCAN_IE_PEDE BIT(28) #define CAN_MCAN_IE_PEDE BIT(28)
#define CAN_MCAN_IE_PEAE BIT(27) #define CAN_MCAN_IE_PEAE BIT(27)
#define CAN_MCAN_IE_WDIE BIT(26) #define CAN_MCAN_IE_WDIE BIT(26)
#define CAN_MCAN_IE_BOE BIT(25) #define CAN_MCAN_IE_BOE BIT(25)
#define CAN_MCAN_IE_EWE BIT(24) #define CAN_MCAN_IE_EWE BIT(24)
#define CAN_MCAN_IE_EPE BIT(23) #define CAN_MCAN_IE_EPE BIT(23)
#define CAN_MCAN_IE_ELOE BIT(22) #define CAN_MCAN_IE_ELOE BIT(22)
#define CAN_MCAN_IE_BEUE BIT(21) #define CAN_MCAN_IE_BEUE BIT(21)
#define CAN_MCAN_IE_BECE BIT(20) #define CAN_MCAN_IE_BECE BIT(20)
@ -186,7 +186,7 @@
#define CAN_MCAN_IE_TEFNE BIT(12) #define CAN_MCAN_IE_TEFNE BIT(12)
#define CAN_MCAN_IE_TFEE BIT(11) #define CAN_MCAN_IE_TFEE BIT(11)
#define CAN_MCAN_IE_TCFE BIT(10) #define CAN_MCAN_IE_TCFE BIT(10)
#define CAN_MCAN_IE_TCE BIT(9) #define CAN_MCAN_IE_TCE BIT(9)
#define CAN_MCAN_IE_HPME BIT(8) #define CAN_MCAN_IE_HPME BIT(8)
#define CAN_MCAN_IE_RF1LE BIT(7) #define CAN_MCAN_IE_RF1LE BIT(7)
#define CAN_MCAN_IE_RF1FE BIT(6) #define CAN_MCAN_IE_RF1FE BIT(6)
@ -198,7 +198,7 @@
#define CAN_MCAN_IE_RF0NE BIT(0) #define CAN_MCAN_IE_RF0NE BIT(0)
/* Interrupt Line Select register */ /* Interrupt Line Select register */
#define CAN_MCAN_ILS 0x058 #define CAN_MCAN_ILS 0x058
#define CAN_MCAN_ILS_ARAL BIT(29) #define CAN_MCAN_ILS_ARAL BIT(29)
#define CAN_MCAN_ILS_PEDL BIT(28) #define CAN_MCAN_ILS_PEDL BIT(28)
#define CAN_MCAN_ILS_PEAL BIT(27) #define CAN_MCAN_ILS_PEAL BIT(27)
@ -231,55 +231,55 @@
#define CAN_MCAN_ILS_RF0NL BIT(0) #define CAN_MCAN_ILS_RF0NL BIT(0)
/* Interrupt Line Enable register */ /* Interrupt Line Enable register */
#define CAN_MCAN_ILE 0x05C #define CAN_MCAN_ILE 0x05C
#define CAN_MCAN_ILE_EINT1 BIT(1) #define CAN_MCAN_ILE_EINT1 BIT(1)
#define CAN_MCAN_ILE_EINT0 BIT(0) #define CAN_MCAN_ILE_EINT0 BIT(0)
/* Global filter configuration register */ /* Global filter configuration register */
#define CAN_MCAN_GFC 0x080 #define CAN_MCAN_GFC 0x080
#define CAN_MCAN_GFC_ANFS GENMASK(5, 4) #define CAN_MCAN_GFC_ANFS GENMASK(5, 4)
#define CAN_MCAN_GFC_ANFE GENMASK(3, 2) #define CAN_MCAN_GFC_ANFE GENMASK(3, 2)
#define CAN_MCAN_GFC_RRFS BIT(1) #define CAN_MCAN_GFC_RRFS BIT(1)
#define CAN_MCAN_GFC_RRFE BIT(0) #define CAN_MCAN_GFC_RRFE BIT(0)
/* Standard ID Filter Configuration register */ /* Standard ID Filter Configuration register */
#define CAN_MCAN_SIDFC 0x084 #define CAN_MCAN_SIDFC 0x084
#define CAN_MCAN_SIDFC_LSS GENMASK(23, 16) #define CAN_MCAN_SIDFC_LSS GENMASK(23, 16)
#define CAN_MCAN_SIDFC_FLSSA GENMASK(15, 2) #define CAN_MCAN_SIDFC_FLSSA GENMASK(15, 2)
/* Extended ID Filter Configuration register */ /* Extended ID Filter Configuration register */
#define CAN_MCAN_XIDFC 0x088 #define CAN_MCAN_XIDFC 0x088
#define CAN_MCAN_XIDFC_LSS GENMASK(22, 16) #define CAN_MCAN_XIDFC_LSS GENMASK(22, 16)
#define CAN_MCAN_XIDFC_FLESA GENMASK(15, 2) #define CAN_MCAN_XIDFC_FLESA GENMASK(15, 2)
/* Extended ID AND Mask register */ /* Extended ID AND Mask register */
#define CAN_MCAN_XIDAM 0x090 #define CAN_MCAN_XIDAM 0x090
#define CAN_MCAN_XIDAM_EIDM GENMASK(28, 0) #define CAN_MCAN_XIDAM_EIDM GENMASK(28, 0)
/* High Priority Message Status register */ /* High Priority Message Status register */
#define CAN_MCAN_HPMS 0x094 #define CAN_MCAN_HPMS 0x094
#define CAN_MCAN_HPMS_FLST BIT(15) #define CAN_MCAN_HPMS_FLST BIT(15)
#define CAN_MCAN_HPMS_FIDX GENMASK(14, 8) #define CAN_MCAN_HPMS_FIDX GENMASK(14, 8)
#define CAN_MCAN_HPMS_MSI GENMASK(7, 6) #define CAN_MCAN_HPMS_MSI GENMASK(7, 6)
#define CAN_MCAN_HPMS_BIDX GENMASK(5, 0) #define CAN_MCAN_HPMS_BIDX GENMASK(5, 0)
/* New Data 1 register */ /* New Data 1 register */
#define CAN_MCAN_NDAT1 0x098 #define CAN_MCAN_NDAT1 0x098
#define CAN_MCAN_NDAT1_ND GENMASK(31, 0) #define CAN_MCAN_NDAT1_ND GENMASK(31, 0)
/* New Data 2 register */ /* New Data 2 register */
#define CAN_MCAN_NDAT2 0x09C #define CAN_MCAN_NDAT2 0x09C
#define CAN_MCAN_NDAT2_ND GENMASK(31, 0) #define CAN_MCAN_NDAT2_ND GENMASK(31, 0)
/* Rx FIFO 0 Configuration register */ /* Rx FIFO 0 Configuration register */
#define CAN_MCAN_RXF0C 0x0A0 #define CAN_MCAN_RXF0C 0x0A0
#define CAN_MCAN_RXF0C_F0OM BIT(31) #define CAN_MCAN_RXF0C_F0OM BIT(31)
#define CAN_MCAN_RXF0C_F0WM GENMASK(30, 24) #define CAN_MCAN_RXF0C_F0WM GENMASK(30, 24)
#define CAN_MCAN_RXF0C_F0S GENMASK(22, 16) #define CAN_MCAN_RXF0C_F0S GENMASK(22, 16)
#define CAN_MCAN_RXF0C_F0SA GENMASK(15, 2) #define CAN_MCAN_RXF0C_F0SA GENMASK(15, 2)
/* Rx FIFO 0 Status register */ /* Rx FIFO 0 Status register */
#define CAN_MCAN_RXF0S 0x0A4 #define CAN_MCAN_RXF0S 0x0A4
#define CAN_MCAN_RXF0S_RF0L BIT(25) #define CAN_MCAN_RXF0S_RF0L BIT(25)
#define CAN_MCAN_RXF0S_F0F BIT(24) #define CAN_MCAN_RXF0S_F0F BIT(24)
#define CAN_MCAN_RXF0S_F0PI GENMASK(21, 16) #define CAN_MCAN_RXF0S_F0PI GENMASK(21, 16)
@ -287,22 +287,22 @@
#define CAN_MCAN_RXF0S_F0FL GENMASK(6, 0) #define CAN_MCAN_RXF0S_F0FL GENMASK(6, 0)
/* Rx FIFO 0 Acknowledge register */ /* Rx FIFO 0 Acknowledge register */
#define CAN_MCAN_RXF0A 0x0A8 #define CAN_MCAN_RXF0A 0x0A8
#define CAN_MCAN_RXF0A_F0AI GENMASK(5, 0) #define CAN_MCAN_RXF0A_F0AI GENMASK(5, 0)
/* Rx Buffer Configuration register */ /* Rx Buffer Configuration register */
#define CAN_MCAN_RXBC 0x0AC #define CAN_MCAN_RXBC 0x0AC
#define CAN_MCAN_RXBC_RBSA GENMASK(15, 2) #define CAN_MCAN_RXBC_RBSA GENMASK(15, 2)
/* Rx FIFO 1 Configuration register */ /* Rx FIFO 1 Configuration register */
#define CAN_MCAN_RXF1C 0x0B0 #define CAN_MCAN_RXF1C 0x0B0
#define CAN_MCAN_RXF1C_F1OM BIT(31) #define CAN_MCAN_RXF1C_F1OM BIT(31)
#define CAN_MCAN_RXF1C_F1WM GENMASK(30, 24) #define CAN_MCAN_RXF1C_F1WM GENMASK(30, 24)
#define CAN_MCAN_RXF1C_F1S GENMASK(22, 16) #define CAN_MCAN_RXF1C_F1S GENMASK(22, 16)
#define CAN_MCAN_RXF1C_F1SA GENMASK(15, 2) #define CAN_MCAN_RXF1C_F1SA GENMASK(15, 2)
/* Rx FIFO 1 Status register */ /* Rx FIFO 1 Status register */
#define CAN_MCAN_RXF1S 0x0B4 #define CAN_MCAN_RXF1S 0x0B4
#define CAN_MCAN_RXF1S_RF1L BIT(25) #define CAN_MCAN_RXF1S_RF1L BIT(25)
#define CAN_MCAN_RXF1S_F1F BIT(24) #define CAN_MCAN_RXF1S_F1F BIT(24)
#define CAN_MCAN_RXF1S_F1PI GENMASK(21, 16) #define CAN_MCAN_RXF1S_F1PI GENMASK(21, 16)
@ -310,69 +310,69 @@
#define CAN_MCAN_RXF1S_F1FL GENMASK(6, 0) #define CAN_MCAN_RXF1S_F1FL GENMASK(6, 0)
/* Rx FIFO 1 Acknowledge register */ /* Rx FIFO 1 Acknowledge register */
#define CAN_MCAN_RXF1A 0x0B8 #define CAN_MCAN_RXF1A 0x0B8
#define CAN_MCAN_RXF1A_F1AI GENMASK(5, 0) #define CAN_MCAN_RXF1A_F1AI GENMASK(5, 0)
/* Rx Buffer/FIFO Element Size Configuration register */ /* Rx Buffer/FIFO Element Size Configuration register */
#define CAN_MCAN_RXESC 0x0BC #define CAN_MCAN_RXESC 0x0BC
#define CAN_MCAN_RXESC_RBDS GENMASK(10, 8) #define CAN_MCAN_RXESC_RBDS GENMASK(10, 8)
#define CAN_MCAN_RXESC_F1DS GENMASK(6, 4) #define CAN_MCAN_RXESC_F1DS GENMASK(6, 4)
#define CAN_MCAN_RXESC_F0DS GENMASK(2, 0) #define CAN_MCAN_RXESC_F0DS GENMASK(2, 0)
/* Tx Buffer Configuration register */ /* Tx Buffer Configuration register */
#define CAN_MCAN_TXBC 0x0C0 #define CAN_MCAN_TXBC 0x0C0
#define CAN_MCAN_TXBC_TFQM BIT(30) #define CAN_MCAN_TXBC_TFQM BIT(30)
#define CAN_MCAN_TXBC_TFQS GENMASK(29, 24) #define CAN_MCAN_TXBC_TFQS GENMASK(29, 24)
#define CAN_MCAN_TXBC_NDTB GENMASK(21, 16) #define CAN_MCAN_TXBC_NDTB GENMASK(21, 16)
#define CAN_MCAN_TXBC_TBSA GENMASK(15, 2) #define CAN_MCAN_TXBC_TBSA GENMASK(15, 2)
/* Tx FIFO/Queue Status register */ /* Tx FIFO/Queue Status register */
#define CAN_MCAN_TXFQS 0x0C4 #define CAN_MCAN_TXFQS 0x0C4
#define CAN_MCAN_TXFQS_TFQF BIT(21) #define CAN_MCAN_TXFQS_TFQF BIT(21)
#define CAN_MCAN_TXFQS_TFQPI GENMASK(20, 16) #define CAN_MCAN_TXFQS_TFQPI GENMASK(20, 16)
#define CAN_MCAN_TXFQS_TFGI GENMASK(12, 8) #define CAN_MCAN_TXFQS_TFGI GENMASK(12, 8)
#define CAN_MCAN_TXFQS_TFFL GENMASK(5, 0) #define CAN_MCAN_TXFQS_TFFL GENMASK(5, 0)
/* Tx Buffer Element Size Configuration register */ /* Tx Buffer Element Size Configuration register */
#define CAN_MCAN_TXESC 0x0C8 #define CAN_MCAN_TXESC 0x0C8
#define CAN_MCAN_TXESC_TBDS GENMASK(2, 0) #define CAN_MCAN_TXESC_TBDS GENMASK(2, 0)
/* Tx Buffer Request Pending register */ /* Tx Buffer Request Pending register */
#define CAN_MCAN_TXBRP 0x0CC #define CAN_MCAN_TXBRP 0x0CC
#define CAN_MCAN_TXBRP_TRP GENMASK(31, 0) #define CAN_MCAN_TXBRP_TRP GENMASK(31, 0)
/* Tx Buffer Add Request register */ /* Tx Buffer Add Request register */
#define CAN_MCAN_TXBAR 0x0D0 #define CAN_MCAN_TXBAR 0x0D0
#define CAN_MCAN_TXBAR_AR GENMASK(31, 0) #define CAN_MCAN_TXBAR_AR GENMASK(31, 0)
/* Tx Buffer Cancellation Request register */ /* Tx Buffer Cancellation Request register */
#define CAN_MCAN_TXBCR 0x0D4 #define CAN_MCAN_TXBCR 0x0D4
#define CAN_MCAN_TXBCR_CR GENMASK(31, 0) #define CAN_MCAN_TXBCR_CR GENMASK(31, 0)
/* Tx Buffer Transmission Occurred register */ /* Tx Buffer Transmission Occurred register */
#define CAN_MCAN_TXBTO 0x0D8 #define CAN_MCAN_TXBTO 0x0D8
#define CAN_MCAN_TXBTO_TO GENMASK(31, 0) #define CAN_MCAN_TXBTO_TO GENMASK(31, 0)
/* Tx Buffer Cancellation Finished register */ /* Tx Buffer Cancellation Finished register */
#define CAN_MCAN_TXBCF 0x0DC #define CAN_MCAN_TXBCF 0x0DC
#define CAN_MCAN_TXBCF_CF GENMASK(31, 0) #define CAN_MCAN_TXBCF_CF GENMASK(31, 0)
/* Tx Buffer Transmission Interrupt Enable register */ /* Tx Buffer Transmission Interrupt Enable register */
#define CAN_MCAN_TXBTIE 0x0E0 #define CAN_MCAN_TXBTIE 0x0E0
#define CAN_MCAN_TXBTIE_TIE GENMASK(31, 0) #define CAN_MCAN_TXBTIE_TIE GENMASK(31, 0)
/* Tx Buffer Cancellation Finished Interrupt Enable register */ /* Tx Buffer Cancellation Finished Interrupt Enable register */
#define CAN_MCAN_TXBCIE 0x0E4 #define CAN_MCAN_TXBCIE 0x0E4
#define CAN_MCAN_TXBCIE_CFIE GENMASK(31, 0) #define CAN_MCAN_TXBCIE_CFIE GENMASK(31, 0)
/* Tx Event FIFO Configuration register */ /* Tx Event FIFO Configuration register */
#define CAN_MCAN_TXEFC 0x0F0 #define CAN_MCAN_TXEFC 0x0F0
#define CAN_MCAN_TXEFC_EFWM GENMASK(29, 24) #define CAN_MCAN_TXEFC_EFWM GENMASK(29, 24)
#define CAN_MCAN_TXEFC_EFS GENMASK(21, 16) #define CAN_MCAN_TXEFC_EFS GENMASK(21, 16)
#define CAN_MCAN_TXEFC_EFSA GENMASK(15, 2) #define CAN_MCAN_TXEFC_EFSA GENMASK(15, 2)
/* Tx Event FIFO Status register */ /* Tx Event FIFO Status register */
#define CAN_MCAN_TXEFS 0x0F4 #define CAN_MCAN_TXEFS 0x0F4
#define CAN_MCAN_TXEFS_TEFL BIT(25) #define CAN_MCAN_TXEFS_TEFL BIT(25)
#define CAN_MCAN_TXEFS_EFF BIT(24) #define CAN_MCAN_TXEFS_EFF BIT(24)
#define CAN_MCAN_TXEFS_EFPI GENMASK(20, 16) #define CAN_MCAN_TXEFS_EFPI GENMASK(20, 16)
@ -380,7 +380,7 @@
#define CAN_MCAN_TXEFS_EFFL GENMASK(5, 0) #define CAN_MCAN_TXEFS_EFFL GENMASK(5, 0)
/* Tx Event FIFO Acknowledge register */ /* Tx Event FIFO Acknowledge register */
#define CAN_MCAN_TXEFA 0x0F8 #define CAN_MCAN_TXEFA 0x0F8
#define CAN_MCAN_TXEFA_EFAI GENMASK(4, 0) #define CAN_MCAN_TXEFA_EFAI GENMASK(4, 0)
#ifdef CONFIG_CAN_MCUX_MCAN #ifdef CONFIG_CAN_MCUX_MCAN